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authorTom Alcorn2020-07-22 12:08:10 -0700
committerGitHub2020-07-22 12:08:10 -0700
commit57c846b1389d507659fae8c7cad092fb83b5f909 (patch)
tree7328291ea8374d9284a5b2d0871a700e4168ed55 /src/main
parent473a13877c60ba9fb13de47542a8397412c2b967 (diff)
Basic model checking API (#1499)
* Add `check(...)` affordance * Add assert (renamed from check and fixed) * Add verification statements * Move formal to experimental.verification * Make test use ChiselStage `generateFirrtl` has been cut from Chisel * Fix newly introduced style warnings * Fix some old style warnings for good measure * Revert "Fix some old style warnings for good measure" This reverts commit 31d51726c2faa4c277230104bd469ff7ffefc890. * Cut scalastyle comments * Cut formal delimiter comments
Diffstat (limited to 'src/main')
-rw-r--r--src/main/scala/chisel3/internal/firrtl/Emitter.scala2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index be8d8f2f..36ac8710 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -80,6 +80,8 @@ private class Emitter(circuit: Circuit) {
val printfArgs = Seq(e.clock.fullName(ctx), "UInt<1>(1)",
"\"" + printf.format(fmt) + "\"") ++ args
printfArgs mkString ("printf(", ", ", ")")
+ case e: Verification => s"${e.op}(${e.clock.fullName(ctx)}, ${e.predicate.fullName(ctx)}, " +
+ s"UInt<1>(1), " + "\"" + s"${printf.format(e.message)}" + "\")"
case e: DefInvalid => s"${e.arg.fullName(ctx)} is invalid"
case e: DefInstance => s"inst ${e.name} of ${e.id.name}"
case w: WhenBegin =>