| Age | Commit message (Expand) | Author |
|---|
| 2017-03-08 | Correct Fill's exception behavior; avoid log2Up | Andrew Waterman |
| 2017-02-16 | Add support for clock and reset scoping (#509) | Jack Koenig |
| 2017-02-08 | Add Analog type | Jack Koenig |
| 2017-02-07 | Name all the things | ducky |
| 2017-02-07 | Rename SeqMem to SyncReadMem. (#490) | Jim Lawson |
| 2017-02-01 | Move backend compilation utilities (#400) | Jim Lawson |
| 2017-01-31 | Fix spelling of ChiselExecutionSuccess | Jack |
| 2017-01-31 | Move blackbox verilog implementations within reach of verilator (#453) | Chick Markley |
| 2017-01-30 | Add shift register with reset (#439) | Stevo |
| 2017-01-27 | Deprecate firrtlToVerilog in favor of compileFirrtlToVerilog (#367) | Jack Koenig |
| 2017-01-27 | Make uselessly public fields in utils private | jackkoenig |
| 2017-01-27 | Provide package-level text to reduce ScalaDoc white space. (#432) | Jim Lawson |
| 2017-01-26 | doesn't lose old firrtl options annotations + transforms (#458) | Angie Wang |
| 2017-01-25 | Better name propagation by macros (#327) | Richard Lin |
| 2017-01-20 | Add Record as new superclass of Bundle (#366) | Jack Koenig |
| 2017-01-20 | Mark Annotation and FixedPoint as experimental (#444) | Chick Markley |
| 2017-01-11 | Merge branch 'master' into fixedPointFromBits | Adam Izraelevitz |
| 2017-01-10 | Make stop() immediately end simulation for Verilator tests (#434) | Jack Koenig |
| 2016-12-15 | Merge branch 'master' into fixedPointFromBits | grebe |
| 2016-12-14 | Final steps for annotations getting from chisel to firrtl (#405) | Chick Markley |
| 2016-12-14 | Change noenq in ReadyValid to use an uninitialized Wire instead of zero (#364) | Jack Koenig |
| 2016-12-13 | Checkpoint | Paul Rigge |
| 2016-12-07 | Support for creating chisel annotations that are consumed by firrtl (#393) | Chick Markley |
| 2016-12-06 | utils scaladoc examples for BitPat through CircuitMath (#398) | Richard Lin |
| 2016-11-29 | Add feature warnings to build, fix feature warnings, fix some documentation (... | Richard Lin |
| 2016-11-23 | Simplify Enum API (#385) | Richard Lin |
| 2016-11-21 | Remove deduplication from Chisel (#347) | Donggyu |
| 2016-11-21 | Deboilerplate the implicit conversions, add support for long.U | ducky |
| 2016-11-21 | Fix Log2 | ducky |
| 2016-11-21 | Fix regex example | ducky |
| 2016-11-21 | Stop confusing scaladoc | ducky |
| 2016-11-21 | better style | ducky |
| 2016-11-21 | Restyle UInt->BitPatComparable | ducky |
| 2016-11-21 | Refactor some code | ducky |
| 2016-11-21 | All remaining automatable regex re-styles | ducky |
| 2016-11-21 | Restyle a lot of test code, mainly with regex | ducky |
| 2016-11-21 | Restyle Bool constructors, move compatibility deprecations into compatibility... | ducky |
| 2016-11-21 | SInt conversion finished, everything builds again | ducky |
| 2016-11-21 | Refactor SInt WIP | ducky |
| 2016-11-21 | Deprecate things, split more things | ducky |
| 2016-11-21 | Break out deprecated literal constructors, refactor all the things! | ducky |
| 2016-11-21 | Move ChiselRange to experimental | ducky |
| 2016-11-21 | Fix open-open range specifier, remove dead code, restyle tests | ducky |
| 2016-11-21 | simple test that range interpolator works with UInt factory method | chick |
| 2016-11-18 | Add support for parameterized BlackBoxes | jackkoenig |
| 2016-11-18 | Change Verilator invocation to use O1 | jackkoenig |
| 2016-11-18 | Shift register enable gates all stages, not just first | Stevo |
| 2016-11-17 | Eliminate some doc warnings | ducky |
| 2016-11-14 | Add SourceInfo.makeMessage to better use SourceInfo in error messages | Jack |
| 2016-10-25 | FixedPoint number support for chisel3 (#328) | Chick Markley |
