| Age | Commit message (Collapse) | Author |
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The old implementation failed to check for width <= -2, and
did the wrong thing when -1 was explicitly passed. Splitting
into two methods avoids the latter issue.
log2Ceil's argument might be 1, so employ a max operator.
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Since the argument is at least 2, this change has no semantic effect.
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Since the argument is at least 2, this change has no semantic effect.
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Both should be zero-width wires.
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Provide a better error message when length < 0.
Change log2Up in log2Ceil, which has no effect, since the argument
is always at least 2.
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It always should throw an exception when n < 0, but in the specific
case of x.isWidthKnown && x.getWidth == 1, it failed to do so.
This commit also changes log2Up in log2Ceil, which has no effect,
since the argument is always at least 2.
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withClockAndReset, withReset, and withClock allow changing the implicit clock and reset.
Module.clock and Module.reset provide access to the current implicit clock and reset.
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Used for stitching Verilog inout through Chisel Modules (from BlackBox
to BlackBox)
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Retain un-deprecated SeqMem in compatibility mode, deprecate in chisel3.
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* Move copyResourceToFile() to BackendCompilationUtilities.
* Move BackendCompilationUtilities into a firrtl util package.
Some of this could be moved into a more general tools package, but since chisel3 already has a dependency on firrtl ...
* Push util down into firrtl so as not to conflict with scala.util.
* Use new createTestDirectory. Fixes #452.
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* Move blackbox verilog implementations within reach of verilator
Blackbox implementers can annotate the modules with information on where to get the source verilog
This API is very lightweight, real work is done in firrtl in companion PR
Added some verilog to BlackBoxTest.v resource for testing
* if a file named black_box_verilog_files.f exists add a
-f black_box_verilog_files.f to the verilog to cpp command
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* [stevo]: add reset initialization to shift register
* [stevo]: better comment
* [stevo]: add tests, fix bug
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Resolves #357
Also remove uses of firrtlToVerilog within chisel3. Invoking Firrtl
programmatically is preferred to on the command line. Update README to
indicate that Firrtl need not be installed.
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Fixing a bug in passing down execution options to firrtl
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* Name propagation
* chiselName everywhere at best-effort level
* Better collision handling
* Allow recursing into inner anonymous functions
* Add for loop and anonymous inner function tests
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Record gives uses the power to create collections of heterogenous elements.
Bundle is a special case of Record that uses reflection to populate the
elements of the collection. Bundle also attempts to implement cloneType whereas
users of Record are required to supply one.
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* Mark Annotation and FixedPoint as experimental
Fix tests and other references to these constructs
* Made experimental imports more specific where possible
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Pass transforms along with Annotations when calling firrtl compiler
This introduces new requirement that firrtl.Transform subclasses (that are associated with an annotation) do not have parameters in their default constructor
Add new test for NoDedup annotation that shows how to annotate a module instance
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* Support for creating chisel annotations that are consumed by firrtl
Update annotation serialization in Driver
Add DiamondAnnotation Spec that illustrates how to do simple annotations
frontEnd must have dependency on firrtl
Add annotation method to Module
Circuit has extra optional parameter that is Seq of Annotations
In Builder add annotation buffer to DynamicContext to store annotations created in modules
Added explicit types on naming api methods to avoid type confusion
Because some names are not available until elaboration create intermediate ChiselAnnotation that
gets turned into a firrtl Annotation after elaboration
In execute pass firrtl text and annotation to firrtl are now passed in through optionManager, though
intermediate file .fir and .anno files are still created for inspection and/or later use
* Somehow missed ChiselAnnotation
* fixes for Jack's review of PR
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Add examples for utils, move examples from individual apply methods to class overview scaladoc
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(#387)
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Get rid of some cruft exposed in #373
This also allows Bits.fromtInt(...) to be removed. Yay!
All old APIs (with some new restrictions, rocket still works fine) are preserved without deprecation in Chisel._, aside from the non-compile-time-checkable Map[] enum constructor which probably should have been deprecated during chisel2. The Map[] enums have been removed from chisel3._ without deprecation.
The new restriction is that nodeType (legacy API) may only be of UInt type with unspecified width. Note that Bits() creates a UInt, and if you can't control the enum values, it makes little sense to specify a bitwidth.
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Remove modName from Module
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compatibility package object
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