Restyle a lot of test code, mainly with regex

13 files changed, 92 insertions, 68 deletions

diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 9d0e266b..625628dd 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -41,6 +41,8 @@ package object Chisel {     // scalastyle:ignore package.object.name
   val assert = chisel3.core.assert
   val stop = chisel3.core.stop
 
+  /** This contains literal constructor factory methods that are deprecated as of Chisel3.
+    */
   trait UIntFactory extends chisel3.core.UIntFactory {
     /** Create a UInt literal with inferred width. */
     def apply(n: String): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
@@ -80,6 +82,8 @@ package object Chisel {     // scalastyle:ignore package.object.name
     def width(width: Width): UInt = apply(width)
   }
 
+  /** This contains literal constructor factory methods that are deprecated as of Chisel3.
+    */
   trait SIntFactory extends chisel3.core.SIntFactory {
     /** Create a SInt type or port with fixed width. */
     def width(width: Int): SInt = apply(Width(width))
@@ -113,6 +117,8 @@ package object Chisel {     // scalastyle:ignore package.object.name
     }
   }
 
+  /** This contains literal constructor factory methods that are deprecated as of Chisel3.
+    */
   trait BoolFactory extends chisel3.core.BoolFactory {
     /** Creates Bool literal.
      */
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 8ac76867..8b5b8a46 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -32,71 +32,89 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   type Element = chisel3.core.Element
   type Bits = chisel3.core.Bits
 
+  /** This contains literal constructor factory methods that are deprecated as of Chisel3.
+    * These will be removed very soon. It's recommended you move your code soon.
+    *
+    * Some recommended regex replacements:
+    * (note: these are not guaranteed to handle all edge cases! check all replacements!)
+    * Bool((true|false)) => $1.B
+    * UInt\(width\s*=\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) => UInt($1.W)
+    * (UInt|SInt|Bits).width\((\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) => $1($2.W)
+    * (U|S)Int\((-?\d+|0[xX][0-9a-fA-F]+)\) => $2.$1
+    * UInt\((\d+|0[xX][0-9a-fA-F]+),\s*(?:width)?\s*=\s*(\d+)\) => $1.U($2.W)
+    * (UInt|SInt)\(([_a-zA-Z][_0-9a-zA-Z]*)\) => $2.as$1
+    */
   trait UIntFactory extends chisel3.core.UIntFactory {
     /** Create a UInt literal with inferred width. */
-    @deprecated("chisel3, will be removed by end of 2016, use n.U")
+    @deprecated("use n.U", "chisel3, will be removed by end of 2016")
     def apply(n: String): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
         chisel3.core.fromStringToLiteral.parsedWidth(n))
     /** Create a UInt literal with fixed width. */
-    @deprecated("chisel3, will be removed by end of 2016, use n.U(width.W)")
+    @deprecated("use n.U(width.W)", "chisel3, will be removed by end of 2016")
     def apply(n: String, width: Int): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
         Width(width))
 
     /** Create a UInt literal with specified width. */
-    @deprecated("chisel3, will be removed by end of 2016, use value.U(width)")
+    @deprecated("use value.U(width)", "chisel3, will be removed by end of 2016")
     def apply(value: BigInt, width: Width): UInt = Lit(value, width)
 
     /** Create a UInt literal with fixed width. */
-    @deprecated("chisel3, will be removed by end of 2016, use value.U(width.W)")
+    @deprecated("use value.U(width.W)", "chisel3, will be removed by end of 2016")
     def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width))
 
     /** Create a UInt with a specified width - compatibility with Chisel2. */
-    @deprecated("chisel3, will be removed by end of 2016, use UInt(width.W)")
+    @deprecated("use UInt(width.W)", "chisel3, will be removed by end of 2016")
     def apply(dir: Option[Direction] = None, width: Int): UInt = apply(Width(width))
 
     /** Create a UInt literal with inferred width.- compatibility with Chisel2. */
-    @deprecated("chisel3, will be removed by end of 2016, use value.U")
+    @deprecated("use value.U", "chisel3, will be removed by end of 2016")
     def apply(value: BigInt): UInt = apply(value, Width())
 
     /** Create a UInt with a specified width */
-    @deprecated("chisel3, will be removed by end of 2016, use UInt(width.W)")
+    @deprecated("use UInt(width.W)", "chisel3, will be removed by end of 2016")
     def width(width: Int): UInt = apply(Width(width))
 
     /** Create a UInt port with specified width. */
-    @deprecated("chisel3, will be removed by end of 2016, use UInt(width)")
+    @deprecated("use UInt(width)", "chisel3, will be removed by end of 2016")
     def width(width: Width): UInt = apply(width)
   }
 
+  /** This contains literal constructor factory methods that are deprecated as of Chisel3.
+    * These will be removed very soon. It's recommended you move your code soon.
+    */
   trait SIntFactory extends chisel3.core.SIntFactory {
     /** Create a SInt type or port with fixed width. */
-    @deprecated("chisel3, will be removed by end of 2016, use SInt(width.W)")
+    @deprecated("use SInt(width.W)", "chisel3, will be removed by end of 2016")
     def width(width: Int): SInt = apply(Width(width))
     /** Create an SInt type with specified width. */
-    @deprecated("chisel3, will be removed by end of 2016, use SInt(width)")
+    @deprecated("use SInt(width)", "chisel3, will be removed by end of 2016")
     def width(width: Width): SInt = apply(width)
 
     /** Create an SInt literal with inferred width. */
-    @deprecated("chisel3, will be removed by end of 2016, use value.S")
+    @deprecated("use value.S", "chisel3, will be removed by end of 2016")
     def apply(value: BigInt): SInt = Lit(value)
     /** Create an SInt literal with fixed width. */
-    @deprecated("chisel3, will be removed by end of 2016, use value.S(width.W)")
+    @deprecated("use value.S(width.W)", "chisel3, will be removed by end of 2016")
     def apply(value: BigInt, width: Int): SInt = Lit(value, width)
 
     /** Create an SInt literal with specified width. */
-    @deprecated("chisel3, will be removed by end of 2016, use value.S(width)")
+    @deprecated("use value.S(width)", "chisel3, will be removed by end of 2016")
     def apply(value: BigInt, width: Width): SInt = Lit(value, width)
 
-    @deprecated("chisel3, will be removed by end of 2016, use value.S")
+    @deprecated("use value.S", "chisel3, will be removed by end of 2016")
     def Lit(value: BigInt): SInt = Lit(value, Width())
 
-    @deprecated("chisel3, will be removed by end of 2016, use value.S(width)")
+    @deprecated("use value.S(width)", "chisel3, will be removed by end of 2016")
     def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width))
   }
 
+  /** This contains literal constructor factory methods that are deprecated as of Chisel3.
+    * These will be removed very soon. It's recommended you move your code soon.
+    */
   trait BoolFactory extends chisel3.core.BoolFactory {
     /** Creates Bool literal.
      */
-    @deprecated("chisel3, will be removed by end of 2016, use x.B")
+    @deprecated("use x.B", "chisel3, will be removed by end of 2016")
     def apply(x: Boolean): Bool = Lit(x)
   }
 
diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala
index 89bb644a..d755b620 100644
--- a/src/main/scala/chisel3/util/Arbiter.scala
+++ b/src/main/scala/chisel3/util/Arbiter.scala
@@ -18,7 +18,7 @@ import chisel3.core.ExplicitCompileOptions.NotStrict
 class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle {
   val in  = Flipped(Vec(n, Decoupled(gen)))
   val out = Decoupled(gen)
-  val chosen = Output(UInt.width(log2Up(n)))
+  val chosen = Output(UInt(log2Up(n).W))
 }
 
 /** Arbiter Control determining which producer has access
@@ -26,8 +26,8 @@ class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle {
 private object ArbiterCtrl {
   def apply(request: Seq[Bool]): Seq[Bool] = request.length match {
     case 0 => Seq()
-    case 1 => Seq(Bool(true))
-    case _ => Bool(true) +: request.tail.init.scanLeft(request.head)(_ || _).map(!_)
+    case 1 => Seq(true.B)
+    case _ => true.B +: request.tail.init.scanLeft(request.head)(_ || _).map(!_)
   }
 }
 
@@ -43,8 +43,8 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
   if (count > 1) {
     val lockCount = Counter(count)
     val lockIdx = Reg(UInt())
-    val locked = lockCount.value =/= UInt(0)
-    val wantsLock = needsLock.map(_(io.out.bits)).getOrElse(Bool(true))
+    val locked = lockCount.value =/= 0.U
+    val wantsLock = needsLock.map(_(io.out.bits)).getOrElse(true.B)
 
     when (io.out.fire() && wantsLock) {
       lockIdx := io.chosen
@@ -53,7 +53,7 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
 
     when (locked) { io.chosen := lockIdx }
     for ((in, (g, i)) <- io.in zip grant.zipWithIndex)
-      in.ready := Mux(locked, lockIdx === UInt(i), g) && io.out.ready
+      in.ready := Mux(locked, lockIdx === i.asUInt, g) && io.out.ready
   } else {
     for ((in, g) <- io.in zip grant)
       in.ready := g && io.out.ready
@@ -63,7 +63,7 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
 class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None)
     extends LockingArbiterLike[T](gen, n, count, needsLock) {
   lazy val lastGrant = RegEnable(io.chosen, io.out.fire())
-  lazy val grantMask = (0 until n).map(UInt(_) > lastGrant)
+  lazy val grantMask = (0 until n).map(_.asUInt > lastGrant)
   lazy val validMask = io.in zip grantMask map { case (in, g) => in.valid && g }
 
   override def grant: Seq[Bool] = {
@@ -71,20 +71,20 @@ class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[
     (0 until n).map(i => ctrl(i) && grantMask(i) || ctrl(i + n))
   }
 
-  override lazy val choice = Wire(init=UInt(n-1))
+  override lazy val choice = Wire(init=(n-1).asUInt)
   for (i <- n-2 to 0 by -1)
-    when (io.in(i).valid) { choice := UInt(i) }
+    when (io.in(i).valid) { choice := i.asUInt }
   for (i <- n-1 to 1 by -1)
-    when (validMask(i)) { choice := UInt(i) }
+    when (validMask(i)) { choice := i.asUInt }
 }
 
 class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None)
     extends LockingArbiterLike[T](gen, n, count, needsLock) {
   def grant: Seq[Bool] = ArbiterCtrl(io.in.map(_.valid))
 
-  override lazy val choice = Wire(init=UInt(n-1))
+  override lazy val choice = Wire(init=(n-1).asUInt)
   for (i <- n-2 to 0 by -1)
-    when (io.in(i).valid) { choice := UInt(i) }
+    when (io.in(i).valid) { choice := i.asUInt }
 }
 
 /** Hardware module that is used to sequence n producers into 1 consumer.
@@ -112,11 +112,11 @@ class RRArbiter[T <: Data](gen:T, n: Int) extends LockingRRArbiter[T](gen, n, 1)
 class Arbiter[T <: Data](gen: T, n: Int) extends Module {
   val io = IO(new ArbiterIO(gen, n))
 
-  io.chosen := UInt(n-1)
+  io.chosen := (n-1).asUInt
   io.out.bits := io.in(n-1).bits
   for (i <- n-2 to 0 by -1) {
     when (io.in(i).valid) {
-      io.chosen := UInt(i)
+      io.chosen := i.asUInt
       io.out.bits := io.in(i).bits
     }
   }
diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala
index e58258c7..9c9909cd 100644
--- a/src/main/scala/chisel3/util/BitPat.scala
+++ b/src/main/scala/chisel3/util/BitPat.scala
@@ -57,7 +57,7 @@ object BitPat {
     */
   def bitPatToUInt(x: BitPat): UInt = {
     require(x.mask == (BigInt(1) << x.getWidth) - 1)
-    UInt(x.value, x.getWidth)
+    x.value.asUInt(x.getWidth.W)
   }
 
   /** Allows UInts to be used where a BitPat is expected, useful for when an
diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala
index 289d27b1..22326972 100644
--- a/src/main/scala/chisel3/util/Bitwise.scala
+++ b/src/main/scala/chisel3/util/Bitwise.scala
@@ -38,10 +38,10 @@ object Fill {
     */
   def apply(n: Int, x: UInt): UInt = {
     n match {
-      case 0 => UInt.width(0)
+      case 0 => UInt(0.W)
       case 1 => x
       case _ if x.isWidthKnown && x.getWidth == 1 =>
-        Mux(x.toBool, UInt((BigInt(1) << n) - 1, n), UInt(0, n))
+        Mux(x.toBool, ((BigInt(1) << n) - 1).asUInt(n.W), 0.U(n.W))
       case _ if n > 1 =>
         val p2 = Array.ofDim[UInt](log2Up(n + 1))
         p2(0) = x
@@ -61,7 +61,7 @@ object Reverse {
       // This esoterica improves simulation performance
       var res = in
       var shift = length >> 1
-      var mask = UInt((BigInt(1) << length) - 1, length)
+      var mask = ((BigInt(1) << length) - 1).asUInt(length.W)
       do {
         mask = mask ^ (mask(length-shift-1,0) << shift)
         res = ((res >> shift) & mask) | ((res(length-shift-1,0) << shift) & ~mask)
diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index d478e10e..83e5feb1 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -10,15 +10,15 @@ import chisel3._
 object Log2 {
   /** Returns the base-2 integer logarithm of the least-significant `width` bits of an UInt.
     *
-    * @note The result is truncated, so e.g. Log2(UInt(13)) === UInt(3)
+    * @note The result is truncated, so e.g. Log2(13.U) === 3.U
     */
   def apply(x: Bits, width: Int): UInt = {
     if (width < 2) {
-      UInt(0)
+      0.U
     } else if (width == 2) {
       x(1)
     } else if (width <= divideAndConquerThreshold) {
-      Mux(x(width-1), UInt(width-1), apply(x, width-1))
+      Mux(x(width-1), UInt((width-1).W), apply(x, width-1))
     } else {
       val mid = 1 << (log2Ceil(width) - 1)
       val hi = x(width-1, mid)
@@ -30,7 +30,7 @@ object Log2 {
 
   /** Returns the base-2 integer logarithm of an UInt.
     *
-    * @note The result is truncated, so e.g. Log2(UInt(13)) === UInt(3)
+    * @note The result is truncated, so e.g. Log2(13.U) === 3.U
     */
   def apply(x: Bits): UInt = apply(x, x.getWidth)
 
diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala
index ba66d667..6d59eaaf 100644
--- a/src/main/scala/chisel3/util/Counter.scala
+++ b/src/main/scala/chisel3/util/Counter.scala
@@ -12,7 +12,7 @@ import chisel3._
   */
 class Counter(val n: Int) {
   require(n >= 0)
-  val value = if (n > 1) Reg(init=UInt(0, log2Up(n))) else UInt(0)
+  val value = if (n > 1) Reg(init=0.U(log2Up(n).W)) else 0.U
 
   /** Increment the counter, returning whether the counter currently is at the
     * maximum and will wrap. The incremented value is registered and will be
@@ -20,14 +20,14 @@ class Counter(val n: Int) {
     */
   def inc(): Bool = {
     if (n > 1) {
-      val wrap = value === UInt(n-1)
-      value := value + UInt(1)
+      val wrap = value === (n-1).asUInt
+      value := value + 1.U
       if (!isPow2(n)) {
-        when (wrap) { value := UInt(0) }
+        when (wrap) { value := 0.U }
       }
       wrap
     } else {
-      Bool(true)
+      true.B
     }
   }
 }
@@ -46,9 +46,9 @@ object Counter
     * maximum and the condition is true).
     *
     * @example {{{
-    * val countOn = Bool(true) // increment counter every clock cycle
+    * val countOn = true.B // increment counter every clock cycle
     * val (counterValue, counterWrap) = Counter(countOn, 4)
-    * when (counterValue === UInt(3)) {
+    * when (counterValue === 3.U) {
     *   ...
     * }
     * }}}
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 2f6effbd..fcda6943 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -32,7 +32,7 @@ object ReadyValidIO {
       * @return    dat.
       */
     def enq(dat: T): T = {
-      target.valid := Bool(true)
+      target.valid := true.B
       target.bits := dat
       dat
     }
@@ -40,7 +40,7 @@ object ReadyValidIO {
     /** Indicate no enqueue occurs.  Valid is set to false, and all bits are set to zero.
       */
     def noenq(): Unit = {
-      target.valid := Bool(false)
+      target.valid := false.B
       // We want the type from the following, not any existing binding.
       target.bits := target.bits.cloneType.fromBits(0.asUInt)
     }
@@ -51,14 +51,14 @@ object ReadyValidIO {
       * @return the data for this device,
       */
     def deq(): T = {
-      target.ready := Bool(true)
+      target.ready := true.B
       target.bits
     }
 
     /** Indicate no dequeue occurs. Ready is set to false
       */
     def nodeq(): Unit = {
-      target.ready := Bool(false)
+      target.ready := false.B
     }
   }
 }
@@ -144,7 +144,7 @@ class QueueIO[T <: Data](gen: T, entries: Int) extends Bundle
   /** I/O to enqueue data, is [[Chisel.DecoupledIO]]*/
   val deq = EnqIO(gen)
   /** The current amount of data in the queue */
-  val count = Output(UInt.width(log2Up(entries + 1)))
+  val count = Output(UInt(log2Up(entries + 1).W))
 
   override def cloneType = new QueueIO(gen, entries).asInstanceOf[this.type]
 }
@@ -177,7 +177,7 @@ extends Module(override_reset=override_reset) {
   val ram = Mem(entries, gen)
   val enq_ptr = Counter(entries)
   val deq_ptr = Counter(entries)
-  val maybe_full = Reg(init=Bool(false))
+  val maybe_full = Reg(init=false.B)
 
   val ptr_match = enq_ptr.value === deq_ptr.value
   val empty = ptr_match && !maybe_full
@@ -201,16 +201,16 @@ extends Module(override_reset=override_reset) {
   io.deq.bits := ram(deq_ptr.value)
 
   if (flow) {
-    when (io.enq.valid) { io.deq.valid := Bool(true) }
+    when (io.enq.valid) { io.deq.valid := true.B }
     when (empty) {
       io.deq.bits := io.enq.bits
-      do_deq := Bool(false)
-      when (io.deq.ready) { do_enq := Bool(false) }
+      do_deq := false.B
+      when (io.deq.ready) { do_enq := false.B }
     }
   }
 
   if (pipe) {
-    when (io.deq.ready) { io.enq.ready := Bool(true) }
+    when (io.deq.ready) { io.enq.ready := true.B }
   }
 
   val ptr_diff = enq_ptr.value - deq_ptr.value
@@ -219,9 +219,9 @@ extends Module(override_reset=override_reset) {
   } else {
     io.count := Mux(ptr_match,
                     Mux(maybe_full,
-                      UInt(entries), UInt(0)),
+                      entries.asUInt, 0.U),
                     Mux(deq_ptr.value > enq_ptr.value,
-                      UInt(entries) + ptr_diff, ptr_diff))
+                      entries.asUInt + ptr_diff, ptr_diff))
   }
 }
 
diff --git a/src/main/scala/chisel3/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala
index 4d816a19..7f715ad4 100644
--- a/src/main/scala/chisel3/util/ImplicitConversions.scala
+++ b/src/main/scala/chisel3/util/ImplicitConversions.scala
@@ -5,6 +5,6 @@ package chisel3.util
 import chisel3._
 
 object ImplicitConversions {
-  implicit def intToUInt(x: Int): UInt = UInt(x)
-  implicit def booleanToBool(x: Boolean): Bool = Bool(x)
+  implicit def intToUInt(x: Int): UInt = chisel3.core.fromIntToLiteral(x).asUInt
+  implicit def booleanToBool(x: Boolean): Bool = x.asBool
 }
diff --git a/src/main/scala/chisel3/util/LFSR.scala b/src/main/scala/chisel3/util/LFSR.scala
index fedbf194..83dc907d 100644
--- a/src/main/scala/chisel3/util/LFSR.scala
+++ b/src/main/scala/chisel3/util/LFSR.scala
@@ -15,9 +15,9 @@ object LFSR16 {
     *
     * @param increment optional control to gate when the LFSR updates.
     */
-  def apply(increment: Bool = Bool(true)): UInt = {
+  def apply(increment: Bool = true.B): UInt = {
     val width = 16
-    val lfsr = Reg(init=UInt(1, width))
+    val lfsr = Reg(init=1.U(width.W))
     when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)) }
     lfsr
   }
diff --git a/src/main/scala/chisel3/util/OneHot.scala b/src/main/scala/chisel3/util/OneHot.scala
index 53ba8c3d..7dd0c68b 100644
--- a/src/main/scala/chisel3/util/OneHot.scala
+++ b/src/main/scala/chisel3/util/OneHot.scala
@@ -35,7 +35,7 @@ object OHToUInt {
   * Multiple bits may be high in the input.
   */
 object PriorityEncoder {
-  def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(UInt(_)))
+  def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(_.asUInt))
   def apply(in: Bits): UInt = apply(in.toBools)
 }
 
@@ -44,9 +44,9 @@ object PriorityEncoder {
 object UIntToOH {
   def apply(in: UInt, width: Int = -1): UInt =
     if (width == -1) {
-      UInt(1) << in
+      1.U << in
     } else {
-      (UInt(1) << in(log2Up(width)-1,0))(width-1,0)
+      (1.U << in(log2Up(width)-1,0))(width-1,0)
     }
 }
 
@@ -55,8 +55,8 @@ object UIntToOH {
   */
 object PriorityEncoderOH {
   private def encode(in: Seq[Bool]): UInt = {
-    val outs = Seq.tabulate(in.size)(i => UInt(BigInt(1) << i, in.size))
-    PriorityMux(in :+ Bool(true), outs :+ UInt(0, in.size))
+    val outs = Seq.tabulate(in.size)(i => (BigInt(1) << i).asUInt(in.size.W))
+    PriorityMux(in :+ true.B, outs :+ 0.U(in.size.W))
   }
   def apply(in: Seq[Bool]): Seq[Bool] = {
     val enc = encode(in)
diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
index f41d789c..00005e3a 100644
--- a/src/main/scala/chisel3/util/Reg.scala
+++ b/src/main/scala/chisel3/util/Reg.scala
@@ -53,7 +53,7 @@ object ShiftRegister
     * @param n number of cycles to delay
     * @param en enable the shift
     */
-  def apply[T <: Data](in: T, n: Int, en: Bool = Bool(true)): T = {
+  def apply[T <: Data](in: T, n: Int, en: Bool = true.B): T = {
     // The order of tests reflects the expected use cases.
     if (n != 0) {
       RegEnable(apply(in, n-1, en), en)
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 3d153a2a..49a6f515 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -41,7 +41,7 @@ object Pipe
       out.bits <> enqBits
       out
     } else {
-      val v = Reg(Bool(), next=enqValid, init=Bool(false))
+      val v = Reg(Bool(), next=enqValid, init=false.B)
       val b = RegEnable(enqBits, enqValid)
       apply(v, b, latency-1)
     }