Deprecate firrtlToVerilog in favor of compileFirrtlToVerilog (#367)

Resolves #357
Also remove uses of firrtlToVerilog within chisel3.  Invoking Firrtl
programmatically is preferred to on the command line.  Update README to
indicate that Firrtl need not be installed.

2 files changed, 16 insertions, 30 deletions

diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index 8b05b159..f4a7d0e5 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -60,9 +60,8 @@ trait BackendCompilationUtilities {
     vf
   }
 
-  /**
-    * like 'firrtlToVerilog' except it runs the process inside the same JVM
- *
+  /** Compile Chirrtl to Verilog by invoking Firrtl inside the same JVM
+    *
     * @param prefix basename of the file
     * @param dir    directory where file lives
     * @return       true if compiler completed successfully
@@ -79,13 +78,13 @@ trait BackendCompilationUtilities {
     }
   }
 
-  /**
-    * compule chirrtl to verilog by using a separate process
- *
+  /** Compile Chirrtl to Verilog by invoking Firrtl on the command line
+    *
     * @param prefix basename of the file
     * @param dir    directory where file lives
-    * @return       true if compiler completed successfully
+    * @return       external process that can invoke Firrtl
     */
+  @deprecated("Use compileFirrtlToVerilog instead", "chisel3")
   def firrtlToVerilog(prefix: String, dir: File): ProcessBuilder = {
     Process(
       Seq("firrtl",
diff --git a/src/main/scala/chisel3/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala
index 83f3c796..bcbb9cd3 100644
--- a/src/main/scala/chisel3/testers/TesterDriver.scala
+++ b/src/main/scala/chisel3/testers/TesterDriver.scala
@@ -21,8 +21,7 @@ object TesterDriver extends BackendCompilationUtilities {
   /** For use with modules that should successfully be elaborated by the
     * frontend, and which can be turned into executables with assertions. */
   def execute(t: () => BasicTester,
-              additionalVResources: Seq[String] = Seq(),
-              runFirrtlasProcess: Boolean = false): Boolean = {
+              additionalVResources: Seq[String] = Seq()): Boolean = {
     // Invoke the chisel compiler to get the circuit's IR
     val circuit = Driver.elaborate(finishWrapper(t))
 
@@ -46,28 +45,16 @@ object TesterDriver extends BackendCompilationUtilities {
       out
     })
 
-    if(runFirrtlasProcess) {
-      // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe
-      if ((firrtlToVerilog(target, path) #&&
-        verilogToCpp(target, target, path, additionalVFiles, cppHarness) #&&
-          cppToExe(target, path)).! == 0) {
-        executeExpectingSuccess(target, path)
-      } else {
-        false
-      }
+    // Compile firrtl
+    if (!compileFirrtlToVerilog(target, path)) {
+      return false
     }
-    else {
-      // Compile firrtl
-      if (!compileFirrtlToVerilog(target, path)) {
-        return false
-      }
-      // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe
-      if ((verilogToCpp(target, target, path, additionalVFiles, cppHarness) #&&
-          cppToExe(target, path)).! == 0) {
-        executeExpectingSuccess(target, path)
-      } else {
-        false
-      }
+    // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe
+    if ((verilogToCpp(target, target, path, additionalVFiles, cppHarness) #&&
+        cppToExe(target, path)).! == 0) {
+      executeExpectingSuccess(target, path)
+    } else {
+      false
     }
   }
   /**