1 files changed, 6 insertions, 7 deletions
diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index 8b05b159..f4a7d0e5 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -60,9 +60,8 @@ trait BackendCompilationUtilities {
     vf
   }
 
-  /**
-    * like 'firrtlToVerilog' except it runs the process inside the same JVM
- *
+  /** Compile Chirrtl to Verilog by invoking Firrtl inside the same JVM
+    *
     * @param prefix basename of the file
     * @param dir    directory where file lives
     * @return       true if compiler completed successfully
@@ -79,13 +78,13 @@ trait BackendCompilationUtilities {
     }
   }
 
-  /**
-    * compule chirrtl to verilog by using a separate process
- *
+  /** Compile Chirrtl to Verilog by invoking Firrtl on the command line
+    *
     * @param prefix basename of the file
     * @param dir    directory where file lives
-    * @return       true if compiler completed successfully
+    * @return       external process that can invoke Firrtl
     */
+  @deprecated("Use compileFirrtlToVerilog instead", "chisel3")
   def firrtlToVerilog(prefix: String, dir: File): ProcessBuilder = {
     Process(
       Seq("firrtl",