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authorJack Koenig2016-12-21 14:33:07 -0800
committerJack Koenig2017-02-08 18:00:32 -0800
commit66a72ff64c46d8a9fdade77223de62b4dcfe2825 (patch)
tree8ff97057072ed7ec1e1c64b3f1db774e2c09f99e /src/main/scala
parent132b80edee2fb8e730d3b6f5eb5f36051a819525 (diff)
Add Analog type
Used for stitching Verilog inout through Chisel Modules (from BlackBox to BlackBox)
Diffstat (limited to 'src/main/scala')
-rw-r--r--src/main/scala/chisel3/internal/firrtl/Emitter.scala1
-rw-r--r--src/main/scala/chisel3/package.scala4
2 files changed, 5 insertions, 0 deletions
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 42bc6c30..eb00e333 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -25,6 +25,7 @@ private class Emitter(circuit: Circuit) {
case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}"
case e: Connect => s"${e.loc.fullName(ctx)} <= ${e.exp.fullName(ctx)}"
case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}"
+ case e: Attach => e.locs.map(_.fullName(ctx)).mkString("attach (", ", ", ")")
case e: Stop => s"stop(${e.clock.fullName(ctx)}, UInt<1>(1), ${e.ret})"
case e: Printf =>
val (fmt, args) = e.pable.unpack(ctx)
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index a5d782ea..a236d3da 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -264,6 +264,10 @@ package object chisel3 { // scalastyle:ignore package.object.name
type RawParam = chisel3.core.RawParam
val RawParam = chisel3.core.RawParam
+ type Analog = chisel3.core.Analog
+ val Analog = chisel3.core.Analog
+ val attach = chisel3.core.attach
+
// Implicit conversions for BlackBox Parameters
implicit def fromIntToIntParam(x: Int): IntParam = IntParam(BigInt(x))
implicit def fromLongToIntParam(x: Long): IntParam = IntParam(BigInt(x))