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path: root/src/main/scala/chisel3/util
AgeCommit message (Expand)Author
2021-05-10implement equal to BitPat. (#1867)Jiuyang Liu
2021-05-09Fix ShiftRegister with 0 delay. (#1903)Jiuyang Liu
2021-05-06add ShiftRegisters to expose register inside ShiftRegister. (#1723)Jiuyang Liu
2021-04-29Scala 2.13 support (#1751)Jack Koenig
2021-03-18Add toString method to BitPat (#1819)Boyang Han
2021-03-11Import memory files inline for Verilog generation (#1805)Carlos Eduardo
2021-03-01Fix conversions between DecoupledIO and IrrevocableIO (#1781)Jerry Zhao
2021-02-26Expose AnnotationSeq to Module. (#1731)Jiuyang Liu
2021-02-08Parametrized Mem- & SyncReadMem-based implementation of the Queue class (#1740)Vladimir Milovanović
2021-02-03Remove Deprecated APIs (#1730)Jiuyang Liu
2021-01-27Fix some typo and using foreach instead of map in BoringUtils (#1755)SoyaOhnishi
2021-01-21Rename MultiIOModule to ModuleJack Koenig
2020-11-16Improve source locators for switch statements. (#1669)Daniel Kasza
2020-10-26Added Force Name API (#1634)Adam Izraelevitz
2020-10-19Enable Cat of Zero Element Vec (#1623)Schuyler Eldridge
2020-10-13ExtModule's lacked support built in support for providing (#1154)Chick Markley
2020-10-01Move Chisel3 to SPDX license conventions (#1604)Chick Markley
2020-09-22Support using switch without importing SwitchContext (#1595)Jack Koenig
2020-09-15make parameters for util modules public (#1452)Albert Chen
2020-09-09Fix load memory from file to work with binary (#1583)HappyQuark
2020-08-13Allow counters to be reset manually (#1527)Josh Bassett
2020-08-11Restore Counter.n API (#1546)Jack Koenig
2020-08-06Update OneHot.scala (#1539)Leigang Kou
2020-07-30Allow a counter to be instantiated using a Scala range (#1515)Josh Bassett
2020-07-29Improved Chisel Naming via Compiler Plugins + Prefixing (#1448)Adam Izraelevitz
2020-07-21Delete outdated scalastyle configuration comments from sourceAlbert Magyar
2020-06-22Canonicalize construction of Decoupled with no payload (#785)Jack Koenig
2020-06-16Move Deprecated LFSR16 to CompatibilitySchuyler Eldridge
2020-06-08Grouping Chisel API (#1073)Adam Izraelevitz
2020-04-20Mux1H: note results unspecified unless exactly one select signal is high (#1397)John Ingalls
2020-04-16Revert "Make uselessly public fields in utils private" (#1417)Adam Izraelevitz
2020-04-10Make Counter emit valid FIRRTL (#1408)Jack Koenig
2020-03-30Java API Documents Linking (#1367)Schuyler Eldridge
2020-02-10Make Queue.irrevocable work properly in chisel3Edward Wang
2020-01-22Change when/switch thunk type to Any (#1308)Schuyler Eldridge
2019-12-18BitPat supports whitespace and underscores, presumably for human readability.chick
2019-11-05Don't use MuxLookup default for full mappingSchuyler Eldridge
2019-10-21Fix BoringUtils.bore for internal boringSchuyler Eldridge
2019-09-13Add requirements to Queue class (#1176)Jack Koenig
2019-09-13Fix Queue.apply for size 0 in chisel3._ code (#1177)Jack Koenig
2019-09-11Move dontTouch, RawModule, and MultiIOModule out of experimental (#1162)Jim Lawson
2019-08-06Avoid when(reset) construct in LFSRAndrew Waterman
2019-08-01Remove anything deprecated since before 3.2Schuyler Eldridge
2019-07-31Fix deprecated Vec usage in chisel3.util.LFSR16Schuyler Eldridge
2019-07-18Add width utility functions to avoid incorrect usage of bare log2Ceil(). (#819)Jim Lawson
2019-06-11Added documentation to Decoupled, Conditionals, Counter (#1015)Adam Izraelevitz
2019-05-20Repackagecore rebase (#1078)Jim Lawson
2019-05-13Fix miscellaneous Scaladoc warningsSchuyler Eldridge
2019-05-12Cleanup loadMemoryFromFile documentationSchuyler Eldridge
2019-05-10Change LFSR16 deprecation from 3.3 -> 3.2Schuyler Eldridge
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