diff options
| author | Albert Magyar | 2020-07-20 12:11:44 -0700 |
|---|---|---|
| committer | Albert Magyar | 2020-07-21 13:06:53 -0700 |
| commit | 7e9f424fb7dcd11c894ceb9f6f049fd9eda80632 (patch) | |
| tree | 1fa15e357d0af7b82316fa2ee659e2e98118488c /src/main/scala/chisel3/util | |
| parent | 4a0e828cfe76e0d3bd6c4a0cc593589fe74ed0ba (diff) | |
Delete outdated scalastyle configuration comments from source
Diffstat (limited to 'src/main/scala/chisel3/util')
| -rw-r--r-- | src/main/scala/chisel3/util/BitPat.scala | 12 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Bitwise.scala | 2 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Conditional.scala | 6 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Decoupled.scala | 4 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala | 1 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/random/LFSR.scala | 4 |
6 files changed, 14 insertions, 15 deletions
diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala index 7c0abdb2..27de9982 100644 --- a/src/main/scala/chisel3/util/BitPat.scala +++ b/src/main/scala/chisel3/util/BitPat.scala @@ -86,16 +86,16 @@ object BitPat { final def =/= (that: BitPat): Bool = macro SourceInfoTransform.thatArg /** @group SourceInfoTransformMacro */ - def do_=== (that: BitPat) // scalastyle:ignore method.name + def do_=== (that: BitPat) (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = that === x /** @group SourceInfoTransformMacro */ - def do_=/= (that: BitPat) // scalastyle:ignore method.name + def do_=/= (that: BitPat) (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = that =/= x final def != (that: BitPat): Bool = macro SourceInfoTransform.thatArg @chiselRuntimeDeprecated @deprecated("Use '=/=', which avoids potential precedence problems", "3.0") - def do_!= (that: BitPat) // scalastyle:ignore method.name + def do_!= (that: BitPat) (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = that != x } } @@ -115,12 +115,12 @@ sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) extends Sou def =/= (that: UInt): Bool = macro SourceInfoTransform.thatArg /** @group SourceInfoTransformMacro */ - def do_=== (that: UInt) // scalastyle:ignore method.name + def do_=== (that: UInt) (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = { value.asUInt === (that & mask.asUInt) } /** @group SourceInfoTransformMacro */ - def do_=/= (that: UInt) // scalastyle:ignore method.name + def do_=/= (that: UInt) (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = { !(this === that) } @@ -128,7 +128,7 @@ sealed class BitPat(val value: BigInt, val mask: BigInt, width: Int) extends Sou def != (that: UInt): Bool = macro SourceInfoTransform.thatArg @chiselRuntimeDeprecated @deprecated("Use '=/=', which avoids potential precedence problems", "3.0") - def do_!= (that: UInt) // scalastyle:ignore method.name + def do_!= (that: UInt) (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = { this =/= that } diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala index 4681b34a..3583b7d1 100644 --- a/src/main/scala/chisel3/util/Bitwise.scala +++ b/src/main/scala/chisel3/util/Bitwise.scala @@ -90,7 +90,7 @@ object Fill { * }}} */ object Reverse { - private def doit(in: UInt, length: Int): UInt = length match { // scalastyle:ignore cyclomatic.complexity + private def doit(in: UInt, length: Int): UInt = length match { case _ if length < 0 => throw new IllegalArgumentException(s"length (=$length) must be nonnegative integer.") case _ if length <= 1 => in case _ if isPow2(length) && length >= 8 && length <= 64 => diff --git a/src/main/scala/chisel3/util/Conditional.scala b/src/main/scala/chisel3/util/Conditional.scala index 7aebc815..4938d075 100644 --- a/src/main/scala/chisel3/util/Conditional.scala +++ b/src/main/scala/chisel3/util/Conditional.scala @@ -12,7 +12,7 @@ import scala.reflect.macros.blackbox._ import chisel3._ @deprecated("The unless conditional is deprecated, use when(!condition){...} instead", "3.2") -object unless { // scalastyle:ignore object.name +object unless { /** Does the same thing as [[when$ when]], but with the condition inverted. */ def apply(c: Bool)(block: => Any) { @@ -56,7 +56,7 @@ class SwitchContext[T <: Element](cond: T, whenContext: Option[WhenContext], lit * @note dummy implementation, a macro inside [[switch]] transforms this into the actual * implementation */ -object is { // scalastyle:ignore object.name +object is { // TODO: Begin deprecation of non-type-parameterized is statements. /** Executes `block` if the switch condition is equal to any of the values in `v`. */ @@ -90,7 +90,7 @@ object is { // scalastyle:ignore object.name * } * }}} */ -object switch { // scalastyle:ignore object.name +object switch { def apply[T <: Element](cond: T)(x: => Any): Unit = macro impl def impl(c: Context)(cond: c.Tree)(x: c.Tree): c.Tree = { import c.universe._ val q"..$body" = x diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index 82511ee5..884235bf 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -107,7 +107,7 @@ object Decoupled */ @chiselName def apply[T <: Data](irr: IrrevocableIO[T]): DecoupledIO[T] = { - require(DataMirror.directionOf(irr.bits) == Direction.Output, "Only safe to cast produced Irrevocable bits to Decoupled.") // scalastyle:ignore line.size.limit + require(DataMirror.directionOf(irr.bits) == Direction.Output, "Only safe to cast produced Irrevocable bits to Decoupled.") val d = Wire(new DecoupledIO(irr.bits)) d.bits := irr.bits d.valid := irr.valid @@ -138,7 +138,7 @@ object Irrevocable * @note unsafe (and will error) on the consumer (output) side of an DecoupledIO */ def apply[T <: Data](dec: DecoupledIO[T]): IrrevocableIO[T] = { - require(DataMirror.directionOf(dec.bits) == Direction.Input, "Only safe to cast consumed Decoupled bits to Irrevocable.") // scalastyle:ignore line.size.limit + require(DataMirror.directionOf(dec.bits) == Direction.Input, "Only safe to cast consumed Decoupled bits to Irrevocable.") val i = Wire(new IrrevocableIO(dec.bits)) dec.bits := i.bits dec.valid := i.valid diff --git a/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala b/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala index 3d14b5c2..92bfcde7 100644 --- a/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala +++ b/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala @@ -123,7 +123,6 @@ object loadMemoryFromFile { * Currently the only non-Verilog based simulation that can support loading memory from a file is treadle but it does * not need this transform to do that. */ -//scalastyle:off method.length class LoadMemoryTransform extends Transform { def inputForm: CircuitForm = LowForm def outputForm: CircuitForm = LowForm diff --git a/src/main/scala/chisel3/util/random/LFSR.scala b/src/main/scala/chisel3/util/random/LFSR.scala index 5b67c509..17e10311 100644 --- a/src/main/scala/chisel3/util/random/LFSR.scala +++ b/src/main/scala/chisel3/util/random/LFSR.scala @@ -103,7 +103,7 @@ object LFSR { lazy val tapsMaxPeriod: Map[Int, Seq[Set[Int]]] = tapsFirst ++ tapsSecond /** First portion of known taps (a combined map hits the 64KB JVM method limit) */ - private def tapsFirst = Map( // scalastyle:off magic.number + private def tapsFirst = Map( 2 -> Seq(Set(2, 1)), 3 -> Seq(Set(3, 2)), 4 -> Seq(Set(4, 3)), @@ -894,6 +894,6 @@ object LFSR { 786 -> Seq(Set(786, 782, 780, 771)), 1024 -> Seq(Set(1024, 1015, 1002, 1001)), 2048 -> Seq(Set(2048, 2035, 2034, 2029)), - 4096 -> Seq(Set(4096, 4095, 4081, 4069)) ) // scalastyle:on magic.number + 4096 -> Seq(Set(4096, 4095, 4081, 4069)) ) } |
