diff options
| author | Jack Koenig | 2021-01-20 13:46:48 -0800 |
|---|---|---|
| committer | Jack Koenig | 2021-01-21 15:36:55 -0800 |
| commit | 5ece5aa8ac2716d66a6ed91e38a978049d8bf250 (patch) | |
| tree | f83353530e836491bb9b770712f1b8ff3dac3942 /src/main/scala/chisel3/util | |
| parent | 616256c35cb7de8fcd97df56af1986b747abe54d (diff) | |
Rename MultiIOModule to Module
Diffstat (limited to 'src/main/scala/chisel3/util')
| -rw-r--r-- | src/main/scala/chisel3/util/Decoupled.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index c6459455..032d731d 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -21,7 +21,7 @@ abstract class ReadyValidIO[+T <: Data](gen: T) extends Bundle { // Compatibility hack for rocket-chip private val genType = (DataMirror.internal.isSynthesizable(gen), chisel3.internal.Builder.currentModule) match { - case (true, Some(module: MultiIOModule)) + case (true, Some(module: Module)) if !module.compileOptions.declaredTypeMustBeUnbound => chiselTypeOf(gen) case _ => gen } |