diff options
| author | Jack Koenig | 2021-01-20 13:46:48 -0800 |
|---|---|---|
| committer | Jack Koenig | 2021-01-21 15:36:55 -0800 |
| commit | 5ece5aa8ac2716d66a6ed91e38a978049d8bf250 (patch) | |
| tree | f83353530e836491bb9b770712f1b8ff3dac3942 /src/main/scala/chisel3 | |
| parent | 616256c35cb7de8fcd97df56af1986b747abe54d (diff) | |
Rename MultiIOModule to Module
Diffstat (limited to 'src/main/scala/chisel3')
| -rw-r--r-- | src/main/scala/chisel3/aop/injecting/InjectingAspect.scala | 4 | ||||
| -rw-r--r-- | src/main/scala/chisel3/util/Decoupled.scala | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala b/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala index f9aaceb1..39590b93 100644 --- a/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala +++ b/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala @@ -2,7 +2,7 @@ package chisel3.aop.injecting -import chisel3.{Module, ModuleAspect, MultiIOModule, RawModule, experimental, withClockAndReset} +import chisel3.{Module, ModuleAspect, RawModule, withClockAndReset} import chisel3.aop._ import chisel3.internal.{Builder, DynamicContext} import chisel3.internal.firrtl.DefModule @@ -63,7 +63,7 @@ abstract class InjectorAspect[T <: RawModule, M <: RawModule]( RunFirrtlTransformAnnotation(new InjectingTransform) +: modules.map { module => val (chiselIR, _) = Builder.build(Module(new ModuleAspect(module) { module match { - case x: MultiIOModule => withClockAndReset(x.clock, x.reset) { injection(module) } + case x: Module => withClockAndReset(x.clock, x.reset) { injection(module) } case x: RawModule => injection(module) } }), dynamicContext) diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index c6459455..032d731d 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -21,7 +21,7 @@ abstract class ReadyValidIO[+T <: Data](gen: T) extends Bundle { // Compatibility hack for rocket-chip private val genType = (DataMirror.internal.isSynthesizable(gen), chisel3.internal.Builder.currentModule) match { - case (true, Some(module: MultiIOModule)) + case (true, Some(module: Module)) if !module.compileOptions.declaredTypeMustBeUnbound => chiselTypeOf(gen) case _ => gen } |