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path: root/src/main/scala/chisel3/util
AgeCommit message (Collapse)Author
2019-05-10Fix LFSR regressionAndrew Waterman
2019-05-09PRNG state UInt->Vec[Bool], make async reset safeSchuyler Eldridge
Changes the internal state of PRNG to use Vec[Bool] instead of UInt. This fixes an @aswaterman identified future problem with asynchronous reset. A register with an asynchronous reset can only be reset to a literal. Previously, an LFSR would store state as a UInt. If it was not parameterized with a seed it should have its least significant bit reset to something to avoid locking up. It's ideal to not reset the full UInt (better test coverage, decreased reset fanout). However, it's difficult to only reset one bit of a UInt. Conversely, it's trivial to reset one bit of a Vec[Bool]. This also moves PRNG/LFSR closer to a canonical representation of their internal state, i.e., it's natural to think of generalizing Vec[Bool] to arbitrary finite fields (Vec[A <: Field]) whereas UInt is tightly coupled to GF2. Minor updates: - Updates/fixes to some scaladoc - Add assertion to period test to make sure LFSR is changing Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-09Deprecate LFSR16, use FibonacciLFSR internallySchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-09Add chisel3.util.random lib w/ LFSR generatorSchuyler Eldridge
Builds out PRNG and LFSR type hierarchy. PRNG is the base class of LFSR of which Galois and Fibonacci are concrete implementations. PRNGs contain state (a UInt) and an update (delta) function. They have a compile-time optional seed to set the PRNG state. The seed/state can also be set at run-time. PRNGs can be run-time parameterized based on how many updates they should do per cycle and whether or not to send the seed through step-count state updates before loading it. (h/t @jwright6323) LFSRs are parameterized in a reduction operation (XOR or XNOR). An LFSR that does NOT have a seed will be automatically initialized to a minimally safe state (set/reset one bit) based on their reduction operation. (h/t @aswaterman) Adds Galois and Fibonacci LFSRs that define appropriate update functions. Companion objects provide helpers to automatically generate maximal period variants. Taps are provide for a very large set of widths. The LFSR companion object provides an apply method to generate a Fibonacci LFSR random variable (like the old LFSR16).
2019-03-21Remove @chiselName from MixedVec (#1045)Richard Lin
2019-03-18Split #974 into two PRs - scalastyle updates (#1037)Jim Lawson
* Update style warnings now that subprojects are aggregated. Use "scalastyle-test-config.xml" for scalastyle config in tests. Enable "_" in method names and accept method names ending in "_=". Re-sync scalastyle-test-config.xml with scalastyle-config.xml * Remove bogus tests that crept in with git add * Add missing import.
2019-03-15Use TransitName for improved Pipe naming (#1024)Schuyler Eldridge
This changes from using the chiselname annotation on Pipe.apply to using an explicit TransitName. This results in an improved name for created valid and bits registers. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-03-14Decouple implementation details from LoadMemoryAnnotation. (#1034)Jim Lawson
2019-03-11ScalaDocs improvement for utils Math, MixedVec (#1019)Richard Lin
2019-02-25Docs for ListLookup (#1028)Richard Lin
Co-Authored-By: ducky64 <elpato25@gmail.com> Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@gmail.com> Co-Authored-By: Edward Wang <edward.c.wang@compdigitec.com>
2019-02-19Add HasBlackBoxPath to BlackBoxUtils.scala (#903)Albert Chen
* Add HasBlackBoxPath trait * Use 'setResource' instead of 'addResource' * Add ScalaDoc
2019-02-19ScalaDoc for Mux (examples added) (#1014)Martin Schoeberl
Co-Authored-By: schoeberl <martin@jopdesign.com> Co-Authored-By: Edward Wang <edward.c.wang@compdigitec.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-19Add Scaladoc for chisel3.util.TransitNameSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-19Util doc lsfr (#1021)Chick Markley
* Update documentation for LSFR16 - Moved bulk of comments to object. - Added an example - Added functional test - example based on section of test * Update documentation for LSFR16 - Moved bulk of comments to object. - Added an example - Added functional test - example based on section of test * Update documentation for LSFR16 - Fixed typos in LFSR - Reduce trials a little - Add test of LFSR period * Update documentation for LSFR16 - Fixed remaining LSFR, arrgh - Removed intellij specific warning suppressor - Fixed comments/scaladoc wording and case. * Update documentation for LSFR16 - Use printable interpolator as example of printing out a Vec
2019-02-19Documentation for Reg utilities (#1018)Martin Schoeberl
2019-02-19ScalaDoc for OneHot (#1016)Martin Schoeberl
2019-02-18Add requirement that Pipe latency >= 0Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-18Add Scaladoc for chisel3.util.PipeSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-18Add Scaldoc for chisel3.util.ValidSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-01-25WireDefault instead of WireInit, keep WireInit around (#986)Martin Schoeberl
2019-01-22Changes to BoringUtils Scaladoc, paramater nameSchuyler Eldridge
This compresses the Scaladoc for BoringUtils slightly by using 120 character lines and removing unnecessary whitespace. This also changes the poorly named "dedup" parameter to the what it actually is: "disableDedup". Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-01-22Fix BoringUtils deduplication bugSchuyler Eldridge
This fixes a bug where BoringUtils non-hierarchical sinks would be deduplicated even when specified that they should not be. h/t @ucbjrl for discovering this! Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-01-21Unify internal (chisel3.core) and external (chisel3 / chisel3.experimental) ↵Richard Lin
Module class names (#994)
2018-12-04Add asBool, deprecate toBoolJack Koenig
2018-12-04Add asBools, deprecate toBoolsJack Koenig
2018-11-02Fix Queue.io.count when entries=1 (#918)Andrew Waterman
Resolves #917
2018-10-29Fix LoadMemoryTransform for Instance Annotations (#914)Schuyler Eldridge
Quickfix for LoadMemoryTransform that gets this to work with Instance Annotations. The new Instance Annotations caused a corner case where a LoadMemoryAnnotation would be duplicated (via update/renaming) and the resulting annotation would differ from the original in only their originalMemoryNameOpt field. This corrects that by having the ChiselLoadMemoryAnnotation also emit the originalMemoryNameOpt field where it did not previously. First part of a fix for freechipsproject/firrtl#922. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-10-12Strong enums (#892)Hasan Genc
* Added new strongly-typed enum construct called "StrongEnum". "StrongEnum" will automatically generate annotations that HDL backends can use to mark components as enums Removed "override val width" constructor parameter from "Element" so that classes with variable widths, like the new strong enums, can inherit from it Changed the parameter types of certain functions, such as "switch", "is", and "LitArg.bindLitArg" from "Bits" to "Element", so that they can take the new strong enums as arguments * Added tests for the new strong enums * Changed StrongEnum exception names and made sure in StrongEnum tests that the correct types of exceptions are thrown * Fixed bug where an enum's global annotation would not be set if it was used in multiple circuits Made styling changes to StrongEnum.scala * Reverted accidental changes to the AnnotatingDiamond test * Changed the API for casting non-literal UInts to enums Added an isValid function that checks whether or not enums have valid values Calling getWidth on an enum's companion object now returns a BigInt instead of an Int * Casting a literal to an enum using the StrongEnum.castFromNonLit(n) function is now simply a wrapper for StrongEnum.apply(n) * Fixed compilation bug * * Added "next" method to EnumType * Renamed "castFromNonLit" to "fromBits" * The FSM example in the test/scala/cookbook now uses StrongEnums * * Changed strong enum API, so that users no longer have to declare both a class and a companion object for each strong enum * Strong enums do not have to be static any longer * * Added scope protections to ChiselEnum.Value so that users cannot call it outside of a ChiselEnum definition * Renamed ChiselEnum.Value type to ChiselEnum.Type so that we can give it a companion object just like UInt and Bool do * * Moved strong enums into experimental package * Non-literal UInts can now be cast to enums with apply() rather than fromBits() * Reduced code-duplication by moving some functions from EnumType and Bits to Element
2018-10-03Modify ReadyValidIO noenq to set the data payload to DontCare. (#902)Steve Burns
* Modify noenq to set the input wires to DontCare.
2018-09-07Put do_* methods in SourceInfoTransformMacro groupSchuyler Eldridge
This places all do_* methods (and two unary methods in SInt and FixedPoint that act like do_* methods) inside the ScalaDoc group "SourceInfoTransformMacro". Classes/objects which need information about this group have an additional bare trait mixed in, `SourceInfoDoc`, that provides information about the group and its priority. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-08-31Support for verilog memory loading. (#840)Chick Markley
* Ability to load memories at simulation startup * first pass * create annotation * create skeleton Transform * Work in progress Building out transform and pass now * Support for LoadMemory annotation * Creates chisel and firrtl LoadMemory annotations * LoadMemoryTransform converts annotation into BlackBox InLine * Simple test that verilog bound modules get created. * Support for LoadMemory annotation * Supports Bundled/multi-field memories * more tests * support for `$readmemh` and `$readmemb` * warns if suffix used in file specification. * Support for LoadMemory annotation * Use standard chisel annotation idiom * Support for LoadMemory annotation * Fixes for @seldridge nits and super-nits * Support for LoadMemory annotation - transform now only runs if emitter is an instance of VerilogEmitter - suffixes on memory text files are now respected - if suffix exists and memory is aggregate, aggregate sub-fields will now be inserted before suffix - every bind module created gets a unique number - this is required when multiple loaded memories appear in a module - this should be generalized for other uses of binding modules * Support for LoadMemory annotation - remove un-needed suffix test * Support for LoadMemory annotation - remove instance walk, now just processes each module * Support for LoadMemory annotation - Move LoadMemoryTransformation into Firrtl for treadle to access it. * Support for LoadMemory annotation - One more bug in suffix handling has been eliminated * Support for LoadMemory annotation - remove unused findModule per jackkoenig - fixed complex test, bad filename edge case * Support for LoadMemory annotation - changed to not use intellij style column alignment for : declarations * Load memory from file Fixes based on @jkoenig review - remove unused BindPrefixFactory - Moved code from CreateBindableMemoryLoaders into to LoadMemoryTransfrom - Made map to find relevant memory annotations faster - Made map to find modules referenced by annotations faster - Made things private that should be private - DefAnnotatedMemorys are no longer referenced, shouldn't be found here. - println of error changed to failed * Loading memories from files - Many changes based on review - move stuff into experimental - clean up annotation manipulation - manage tests better - use more standard practices for transform * Loading memories from files - More review changes - Move doc from annotation to the object apply method that generates the annotation - Make scalastyle directives more specific - Use more efficient collect to generate name to module map - Made lines obey style length limit - a couple of cleanups of imports in tests - removed some commented out code - optimized checking for lines using .exists - use _ for unused variable in match
2018-08-23Add FlattenInstance APISchuyler Eldridge
This adds a new trait, FlattenInstance, to chisel3.util.experimental. When mixed into a module or a specific instance this trait will "flatten", i.e., "inline that module and all of its submodules". This includes testing (additions to InlineSpec) and ScalaDoc documentation. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-08-23Add InlineInstance APISchuyler Eldridge
This adds a new trait, InlineInstance, to chisel3.util.experimental. This trait, when mixed into a specific module or instance, will "inline" that module, i.e., "collapse a module while preserving it's submodules." This includes testing (InlineSpec) and ScalaDoc documentation. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-08-22Implement varargs MixedVec APIEdward Wang
2018-08-22Make MixedVec wire init consistent with VecInitEdward Wang
2018-08-22Remove dynamic indexing for nowEdward Wang
We can sometimes shim with other workarounds like VecInit or manually creating a mux
2018-08-22MixedVec: clarify dynamic indexing of heterogeneous elementsEdward Wang
2018-08-22Remove redundant := methodEdward Wang
2018-08-22MixedVec implementationEdward Wang
2018-08-07BoringUtils / Synthesizable Cross Module References (#718)Schuyler Eldridge
This adds an annotator that provides a linkage to the FIRRTL WiringTransform. This enables synthesizable cross module references between one source and multiple sinks without changing IO (the WiringTransform bores through the hierarchy). Per WiringTransform, this will connect sources to their closest sinks (as determined by BFS) or fail if ownership is indeterminate. Make TesterDriver.execute work like Driver.execute: - annotations are included when running FIRRTL - custom transforms are run automatically Also, add a bore method to BoringUtils that allows you to do one source to multi-sink mapping in a single call. This adds a test that this is doing the same thing as the equivalent call via disjoint addSink/addSource. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-07-31Cleanup implicit conversions (#868)Jack Koenig
2018-07-06Undeprecate log2Up and log2Down (#846)Jack Koenig
They should not be deprecated until zero-width wires actually work
2018-07-04Prefer litValue, eliminate litToBigIntducky
2018-07-04Style fixesducky
2018-07-04work on new style literal accessorsducky
2018-06-25Correcting documentation errors in Arbiter.scala (#839)Brendan Sweeney
Documentation for example had parameters in wrong order, and was missing @param. Additionally, it was lacking a module wrapper. This has been corrected.
2018-06-18Fixed UIntToOH(x, 1) invocation with x.width == 0 (#778)Wesley W. Terpstra
2018-05-24Fix UIntToOH for output widths larger than 2^(input width) (#823)Andrew Waterman
* Add test for UIntToOH * Pad UIntToOH inputs to support oversized output widthds * Optimize Bits.pad in case of known widths * Add missing import and fix test in OneHotMuxSpec
2018-02-28Refactor Annotations (#767)Jack Koenig
* Generalize ChiselAnnotation This allows us to delay creation of Annotations till elaboration is complete. Also update all annotation-related code. * Add RunFirrtlTransform Use a Chisel-specific RunFirrtlTransform API to preserve behavior of old ChiselAnnotation (now called ChiselLegacyAnnotation) * Use unique test directories in ChiselRunners.compile
2018-02-21Support zero-entry queues (but not for irrevocable) (#780)Andrew Waterman
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