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path: root/src/main/scala/chisel3/util
AgeCommit message (Expand)Author
2021-08-12Pass truth table to espresso using stdin instead of temp fileBoyang Han
2021-08-03Added flush capability to Queue (#2030)anniej-sifive
2021-07-14Espresso Decoder (#1964)Jiuyang Liu
2021-06-16Add computational complexity analysisBoyang Han
2021-06-16Refactor to a more `scala` formBoyang Han
2021-06-16Merge minimized table before return as a TruthTableBoyang Han
2021-06-16implement QMC.Boyang Han
2021-06-16Apply Jack's Review Jiuyang Liu
2021-06-16add documentation for DecodeTableAnnotation.Jiuyang Liu
2021-06-16remove all timeouts by review.Jiuyang Liu
2021-06-16async decoder with 5 seconds timeout.Jiuyang Liu
2021-06-16add a simple decoder API.Jiuyang Liu
2021-06-16implement abstract Minimizer as a general API.Jiuyang Liu
2021-06-16fix for 2.13Jiuyang Liu
2021-06-16TruthTable can merge same inputs now.Jiuyang Liu
2021-06-16implement DecodeTableAnnotation for decode table caching.Jiuyang Liu
2021-06-16implement TruthTable to represent a decode table.Jiuyang Liu
2021-06-10Stop Emitting BlackBoxResourceAnno (#1954)Schuyler Eldridge
2021-05-25throw exception if BitPat width is 0 (#1920)Jiuyang Liu
2021-05-20Implement PLA (#1912)Jiuyang Liu
2021-05-10implement equal to BitPat. (#1867)Jiuyang Liu
2021-05-09Fix ShiftRegister with 0 delay. (#1903)Jiuyang Liu
2021-05-06add ShiftRegisters to expose register inside ShiftRegister. (#1723)Jiuyang Liu
2021-04-29Scala 2.13 support (#1751)Jack Koenig
2021-03-18Add toString method to BitPat (#1819)Boyang Han
2021-03-11Import memory files inline for Verilog generation (#1805)Carlos Eduardo
2021-03-01Fix conversions between DecoupledIO and IrrevocableIO (#1781)Jerry Zhao
2021-02-26Expose AnnotationSeq to Module. (#1731)Jiuyang Liu
2021-02-08Parametrized Mem- & SyncReadMem-based implementation of the Queue class (#1740)Vladimir Milovanović
2021-02-03Remove Deprecated APIs (#1730)Jiuyang Liu
2021-01-27Fix some typo and using foreach instead of map in BoringUtils (#1755)SoyaOhnishi
2021-01-21Rename MultiIOModule to ModuleJack Koenig
2020-11-16Improve source locators for switch statements. (#1669)Daniel Kasza
2020-10-26Added Force Name API (#1634)Adam Izraelevitz
2020-10-19Enable Cat of Zero Element Vec (#1623)Schuyler Eldridge
2020-10-13ExtModule's lacked support built in support for providing (#1154)Chick Markley
2020-10-01Move Chisel3 to SPDX license conventions (#1604)Chick Markley
2020-09-22Support using switch without importing SwitchContext (#1595)Jack Koenig
2020-09-15make parameters for util modules public (#1452)Albert Chen
2020-09-09Fix load memory from file to work with binary (#1583)HappyQuark
2020-08-13Allow counters to be reset manually (#1527)Josh Bassett
2020-08-11Restore Counter.n API (#1546)Jack Koenig
2020-08-06Update OneHot.scala (#1539)Leigang Kou
2020-07-30Allow a counter to be instantiated using a Scala range (#1515)Josh Bassett
2020-07-29Improved Chisel Naming via Compiler Plugins + Prefixing (#1448)Adam Izraelevitz
2020-07-21Delete outdated scalastyle configuration comments from sourceAlbert Magyar
2020-06-22Canonicalize construction of Decoupled with no payload (#785)Jack Koenig
2020-06-16Move Deprecated LFSR16 to CompatibilitySchuyler Eldridge
2020-06-08Grouping Chisel API (#1073)Adam Izraelevitz
2020-04-20Mux1H: note results unspecified unless exactly one select signal is high (#1397)John Ingalls
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