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Partially resolves #164
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@aswaterman closes #156
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The old blackbox behavior still emitted extmodules that have a
clk, reset pin and prepended all io's with io_ (ultimately). Most
verilog modules do not follow this distinction (or use a slightly
different name for clock and so on).
Thus, instead BlackBox has been rewritten to not assume a clk or
reset pin. Instead, the io Bundle specified is flattened directly
into the Module.ports declaration. The tests have been rewritten
to compensate for this. Also, added a test that uses the clock pin.
As a secondary change, the _clock and _reset module parameters were
bad for two reasons. One, they used null as a default, which is a
scala best practices violation. Two, they were just not good names.
Instead the primary constructor has been rewritten to take an
Option[Clock] called override_clock and an Option[Bool] called
override_reset, which default to None. (Note how the getOrElse call
down below is much more natural now.)
However, users may not want to specify the Some(their_clock) so I
also added secondary constructors that take parameters named clock
and reset and wrap them into Some calls into the primary constructor.
This is a better UX because now you can just stipulate clock=blah in
instantiation of that module in symmetry with using the clock in the
definition of the module by invoking clock.
PS: We could also back out of allowing any overrides via the Module
constructor and just require the instantiating Module to do
submodule.clock := newclock, etc.
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Often times the scala runtime reflection fails to find an appropriate
name for a given net. This commit tries to partially ameliorate the
issue by exposing a suggestName function onto HasId (i.e. Module, Data)
that the user can call to 'suggest' a name.
Only the first suggestion is taken so repeated calls to suggestName will
not change the name for that node. This type of name exposure is
slightly risky as there is a chance the same name is suggested in the
same namespace. Thus, naming within a Module occurs in two passes:
The suggestion phase is when the user calls suggestName, etc. Near the
'end,' the Module uses runtime reflection to suggest names as well.
The forcing phase is when all the nodes are run through and a name is
'forced' onto them, using the namespace to suggest alternatives if the
desired one is taken. If no suggestion is present, the default name is
T, as before.
Second, there is an issue that commonly comes up when a component
library creates intermediate logic and then only returns a piece, or
even a piece of a piece (like part of a module IO). Any names suggested
by the Module by reflection onto that return value are either lost or
not fully applied. This issue is resolved by TransitName. TransitName
attaches a hook to the suggestName function of a HasId. With that hook,
any time suggestName is called on the hooked ID, that name suggestion is
also applied to other nodes.
For example, if Queue(in) is called, then any attempts to name the
returned output DecoupledIO will actually translate to naming attempts
on the backing Queue.
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One could make an argument for disallowing n=0, too, but HW generators
will benefit from our leniency.
Closes #107. Thanks @jackkoenig
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Mathematically, we should also reject 0, like log2Ceil does. But accepting
0 and returning 1 is more in the spirit of the special case for widths.
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This would ultimately get DCE'd, but it's easy enough to not
generate the dead code in the first place.
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- Remove power-of-2 restriction on count
- Avoid redundancy between lockIdx and chosen signals, reducing area
- Infer locked from lockCount, rather than maintaining separate state
- Reduce FIRRTL node count in several places
- Special-case simple Arbiter, which avoids serializing the computation
of io.chosen with io.out.valid/bits. This lops off a few FO4 delays
at no area cost, and actually reduces area if io.chosen isn't used.
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It was never meant to be a public API, and the implementation left
something to be desired.
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It doesn't really make sense to create a one-hot result then follow it
with a decoder. It's more performant to use a PriorityEncoder followed
by a comparator. Discourage the former by returning Seq, not Vec.
In Chisel2, it seems the return type was originally Seq, but was at some
point inadvertently changed to Vec.
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for DeqIO and EnqIO initialization is likely to change.
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Make the corresponding test run faster by giving it a Counter.
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Gate assert, printf, stop by reset
Fix testbenches that never worked
Change simulation prints to display cycle at which test was signaled to end, not when simulator stops
Better documentation for Counter
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