diff options
| author | ducky | 2015-12-11 14:25:42 -0800 |
|---|---|---|
| committer | ducky | 2015-12-11 17:16:30 -0800 |
| commit | dbd072172f6312893e1922e48ed768ae0fab9a89 (patch) | |
| tree | c3a0f10dd286ae2bba50c31b987ab39c45189898 /src/main/scala/Chisel/util | |
| parent | bffc67c2bbeb107d2ff9903aa35e85fbb7da73f9 (diff) | |
Refactor tests to use stop() and assert() instead of io.error/io.done
Gate assert, printf, stop by reset
Fix testbenches that never worked
Change simulation prints to display cycle at which test was signaled to end, not when simulator stops
Better documentation for Counter
Diffstat (limited to 'src/main/scala/Chisel/util')
| -rw-r--r-- | src/main/scala/Chisel/util/Counter.scala | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/util/Counter.scala b/src/main/scala/Chisel/util/Counter.scala index e4a8e95b..356cedc8 100644 --- a/src/main/scala/Chisel/util/Counter.scala +++ b/src/main/scala/Chisel/util/Counter.scala @@ -3,10 +3,14 @@ package Chisel /** A counter module - * @param n The maximum value of the counter, does not have to be power of 2 + * @param n number of counts before the counter resets (or one more than the + * maximum output value of the counter), need not be a power of two */ class Counter(val n: Int) { val value = if (n == 1) UInt(0) else Reg(init=UInt(0, log2Up(n))) + /** Increment the counter this cycle. Returns whether the counter is at its + * maximum (and will wrap around on the next inc() call). + */ def inc(): Bool = { if (n == 1) { Bool(true) |
