| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-05-05 | Move Chisel API into separate chiselFrontend compilation unit in preparation ↵ | ducky | |
| for source locator macros | |||
| 2016-05-04 | Remove dependences from Chisel core on Chisel utils | Andrew Waterman | |
| Partially resolves #164 | |||
| 2016-04-26 | Scalastyle fixes and "ignores". - No functional changes. | Jim Lawson | |
| 2016-04-05 | Make Wire(init = x) behave the same as Wire(t = x) := x | Andrew Waterman | |
| There's a separate debate to be had about whether we want to default-initialize Wires to invalid. This patch just fixes the implementation of the previous, unsafe approach, which was usually, but not always, defaulting to invalid. | |||
| 2016-03-31 | Fix fromBits for this.width > that.width | Andrew Waterman | |
| Sign- or zero-extend the argument to match. | |||
| 2016-02-08 | Add Flipped trait that flips an Aggregate | Andrew Waterman | |
| 2016-01-28 | Use FIRRTL is invalid construct | Andrew Waterman | |
| 2016-01-23 | Move firrtl subpackage to inside internal subpackage. | jackkoenig | |
| 2016-01-16 | Allow Wire() to be called from parameterized functions | Andrew Waterman | |
| Accomplish this by avoiding default-null parameters on the apply methods. | |||
| 2016-01-15 | flatten should return Seq[Bits], not Seq[UInt] | Andrew Waterman | |
| Calling toBits inside of flatten makes asInput/asOutput/asDirectionless fail on SInts. Also, the abstract type Data was already defining it to return Seq[Bits], so this change didn't really change the API. | |||
| 2015-12-06 | Split internal and FIRRTL packages | ducky | |
| 2015-11-02 | Remove implementation details from scaladoc. | ducky | |
| You didn't want it, so Imma getting rid of it... | |||
| 2015-10-29 | Resolve review todos for Data.scala | ducky | |
| 2015-10-26 | Break Core.scala into bite-sized pieces | ducky | |
