| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-05-05 | Move Chisel API into separate chiselFrontend compilation unit in preparation ... | ducky |
| 2016-05-04 | Remove dependences from Chisel core on Chisel utils | Andrew Waterman |
| 2016-04-26 | Scalastyle fixes and "ignores". - No functional changes. | Jim Lawson |
| 2016-04-05 | Make Wire(init = x) behave the same as Wire(t = x) := x | Andrew Waterman |
| 2016-03-31 | Fix fromBits for this.width > that.width | Andrew Waterman |
| 2016-02-08 | Add Flipped trait that flips an Aggregate | Andrew Waterman |
| 2016-01-28 | Use FIRRTL is invalid construct | Andrew Waterman |
| 2016-01-23 | Move firrtl subpackage to inside internal subpackage. | jackkoenig |
| 2016-01-16 | Allow Wire() to be called from parameterized functions | Andrew Waterman |
| 2016-01-15 | flatten should return Seq[Bits], not Seq[UInt] | Andrew Waterman |
| 2015-12-06 | Split internal and FIRRTL packages | ducky |
| 2015-11-02 | Remove implementation details from scaladoc. | ducky |
| 2015-10-29 | Resolve review todos for Data.scala | ducky |
| 2015-10-26 | Break Core.scala into bite-sized pieces | ducky |
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index : chiselX | |
| Chisel with SFC compatibility |
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