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authorJim Lawson2016-04-26 11:06:16 -0700
committerJim Lawson2016-04-26 11:06:16 -0700
commit09958f63470697188e1ed1a01c7ea39b8c56e7ef (patch)
tree9c0d8ef8d69cbe74b5e56e8474f0304aacdadc6b /src/main/scala/Chisel/Data.scala
parent19046381ae319915c4e8fff7b108e6b5dd100509 (diff)
Scalastyle fixes and "ignores". - No functional changes.
Diffstat (limited to 'src/main/scala/Chisel/Data.scala')
-rw-r--r--src/main/scala/Chisel/Data.scala10
1 files changed, 7 insertions, 3 deletions
diff --git a/src/main/scala/Chisel/Data.scala b/src/main/scala/Chisel/Data.scala
index ac3bd9ab..3fa3dc20 100644
--- a/src/main/scala/Chisel/Data.scala
+++ b/src/main/scala/Chisel/Data.scala
@@ -94,8 +94,11 @@ abstract class Data(dirArg: Direction) extends HasId {
var i = 0
val wire = Wire(this.cloneType)
val bits =
- if (n.width.known && n.width.get >= wire.width.get) n
- else Wire(n.cloneTypeWidth(wire.width), init = n)
+ if (n.width.known && n.width.get >= wire.width.get) {
+ n
+ } else {
+ Wire(n.cloneTypeWidth(wire.width), init = n)
+ }
for (x <- wire.flatten) {
x := bits(i + x.getWidth-1, i)
i += x.getWidth
@@ -124,8 +127,9 @@ object Wire {
val x = Reg.makeType(t, null.asInstanceOf[T], init)
pushCommand(DefWire(x))
pushCommand(DefInvalid(x.ref))
- if (init != null)
+ if (init != null) {
x := init
+ }
x
}
}