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The compiler plugin obviates the need for using stack traces to
determine outer objects in autoclonetype. When the plugin was used to
compile a given Bundle, it will no longer collect a stack trace upon
construction. This should have massive benefits to elaboration runtime.
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Not a Pokémon
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* Handle MemTypeBinding in Analog
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Fix stack trace trimming across ChiselStage
Fix bug in stack trace trimming behavior. Now, the following is what
happens:
1. The Builder, if catching accumulated errors, will now throw a
ChiselException with a Scala-trimmed Stack trace. Previously, this
would throw the full excpetion.
2. The Elaborate phase handles stack trace trimming. By default, any
Throwable thrown during elaboration will have its stack
trace *mutably* trimmed and is rethrown. A logger.error is printed
stating that there was an error during elaboration and how the user
can turn on the full stack trace. If the --full-stacktrace option
is on, then the Throwable is not caught and only the first
logger.error (saying that elaboration failed) will be printed.
3. ChiselStage (the class), ChiselStage$ (the object), and ChiselMain
all inherit the behavior of (2).
Mutable stack trace trimming behavior is moved into an implicit
class (previously this was defined on ChiselException only) so this
can be applied to any Throwable.
No StageErrors are now thrown anymore. However, StageErrors may still
be caught by ChiselMain (since it is a StageMain).
Testing is added for ChiselMain, ChiselStage, and ChiselStage$ to test
all this behavior.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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No longer create a pointer from parent to every HasId, only do it by
default for BaseModules and MemBases. Add pointer from parent to Data
upon binding the Data.
* Add MemTypeBinding for port types of Mems
This binding is similar to the SampleElementBinding for Vecs in that
these Data are not truly hardware, but are represented in the FIRRTL IR
and thus need some representation.
* Call _onModuleClose on unbound Records
This maintains some corner-case behavior that is nevertheless relied
upon. It ensures that refs are set for the elements of Records, even if
they are not bound to any real hardware.
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* Update reported width from div/rem to match FIRRTL results
* Add tests for width of % and / on UInt and SInt
* Add loop-based test for known UInt/SInt op result widths
Co-authored-by: Jack Koenig <koenig@sifive.com>
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This is a nit fix. no logic is changed.
* Rename `typeName` to `enumTypeName` in ScalaDoc
* Add return type at public method
* Rename `enum_records` into `enumRecords` to retain name consistency
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Co-authored-by: Megan Wachs <megan@sifive.com>
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Chisel projects no longer need -Xsource:2.11 when compiling with Scala
2.12.
Autowrapping of "val io" for compatibility mode Modules is now
implemented using reflection instead of calling the virtual method.
Also move Chisel.BlackBox to new chisel3.internal.LegacyBlackBox
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This PR revert #1480, but keep the test.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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This is useful for libraries to guard operations implemented via
annotations or BlackBoxes by the current when predicate
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serialize properly) (#1714)
* Add (failing) Test for Data toTarget calls
Add scaladoc and clean up test
* Builder: don't let .toTarget pass if it won't be able to deserialize properly later
* Update src/test/scala/chiselTests/ReferenceTargetSpec.scala
* Rename and simplify tests for literal toTarget
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(#1670)
* Builder: use LazyLogging.logger.warn to print elaboration message
* add deprecation for chisel3.internal.ErrorLog.info.
* add test to check elaboration message still exist.
Co-authored-by: Kevin Laeufer <kevin.laeufer@sifive.com>
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Implemented by folding Element.ref into Data.ref. Element.ref had
special handling for literals, but because Bundles can also be literals,
there were code paths that tried to get the ref of a Bundle literal
which was non-existent. Now, all literals are handled together.
Because FIRRTL does not have support for Bundle literals, Bundle literal
refs are implemented by materializing a Wire.
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* Refine autonaming to have more intuitive behavior
Last name in an Expression wins, while the first Statement to name wins.
This is done via checking the _id of HasIds during autonaming and only
applying a name if the HasId was created in the scope of autonaming.
There is no change to .autoSeed or .suggestName behavior.
Behavior of chisel3-plugins from before this change is maintained.
* Update docs with naming plugin changes
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This is a refinement of the assertion added in #1616 then removed in
#1654. Because Records now set the refs of children upon binding,
later, unbound Records could incorrectly override the refs. The first
set should win.
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It causes issues for some legal (if awkward) patterns. A larger refactor
of when refs are set could reinstate this check.
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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This requires a combination of things, but it happens to be a
combination used by Diplomacy in Rocket Chip. It must be a Record in
compatibility code with Vecs as fields and a mix of components with and
without set directions.
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* Bugfix - module name collision for injecting aspect
* Fixed mechanism to avoid module name collisions
* Added comments for reviewer feedback
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Use Data refs for name prefixing with aggregate elements
Vecs set the refs of their elements upon construction of those elements.
In the past, Records haven't set their elements refs until module close,
but it can be done sooner. Doing it upon binding means that refs will at
least be available for Records used in hardware elements. Since only
bound Data can be connected to anyway, Aggregate elements being
connected to will always have a ref which we can then use for creating
naming prefixes.
* Add tighter correctness checks
* Handle more cases in connection prefixing
Add support for forcing setRef to override a previous setting. This
is only used by BlackBox ports which need to drop their io prefix.
Also add a Try() around Data.bindingToString which sometimes throws
exceptions when being used to .toString a Data in an error message.
* Strip trailing spaces in names in compiler plugin
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This allows for sharing of the prefix stacks between Data, and removes a
boxing per prefix stack element that is no longer necessary.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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* Return 0.U for asUInt of a zero-element Seq
Add a condition to SeqUtils.asUInt to have it return an unspecified
width 0.U when applied to an empty sequence. This enables the ability
to do a Cat of a zero-element sequence.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Test elaboration of Cat on zero-element Seq
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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Package chisel3 was not properly marked as an internal package so source
locators in reported errors would point to files like Bits.scala.
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Fixes #1606
Previously, the Data itself would be put on the prefix stack and its
full name would be used as the prefix for subsequent names. This meant
that prefixes would grow quadratically as the prefix is present both on
the Data pushed to the stack, and on the stack itself. This is fixed by
just using the "local" name of the Data being pushed on the stack.
A related issue is deferring the name resolution. This led to unintuitive
behavior when the name of a Data used as a prefix is overridden later
(usually when the Data is a return value). The overriding name would
show up in prefixes twice instead of once. It is much more intuitive to
grab the name at the moment of the connection creating the prefix rather
than deferring to later.
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Change source and other relevant files to use SPDX license
LICENSE file moved from src/ to ./
Changed license file to refer to this per recommendation
using_spdx_license_list_short_identifiers
WARNING: Tests fail with as of yet undiagnosed error
```
[error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15
[error] Failed tests:
[error] chiselTests.QueueSpec
[error] examples.VendingMachineGeneratorSpec
[error] chiselTests.HarnessSpec
[error] chiselTests.ConnectSpec
[error] chiselTests.aop.SelectSpec
[error] chiselTests.PopCountSpec
[error] chiselTests.CloneModuleSpec
[error] (Test / test) sbt.TestsFailedException: Tests unsuccessful
[error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM
sbt:chisel3>
```
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* Added documentation. Bugfix in plugin. Moved plugin APIs to separate package
* Revert reg naming behavior (omit underscore)
* Added documentation and a test
* Addressed reviewer feedback.
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Test all cases in ParameterizedOneHotTesters
Co-authored-by: Jack Koenig <koenig@sifive.com>
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Leverages chiselRuntimeDeprecated infrastructure. As such it is not
currently suppressible.
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* Deprecate Module.io and BlackBox.io
This is a step toward unification of Module with MultiIOModule.
The future of BlackBox is a bit less clear, but its existing API can be
maintained without the io virtual method.
The trickier API to maintain is auto-IO wrapping for compatibility
Modules and BlackBoxes. This will probably require reflection to support
once the io virtual method is removed.
* Improve deprecation warning for io
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* Fixed the aspect as parent bug in Data and MonoConnect
* refactored and cleaned up finding an aspect parent
* Added aspect fix to the BiConnect class
* added unit test for manipulating submodules via aspects
* Refactored to move determination of proper parent to Builder and made logic simpler in MonoConnect, Data, and BiConnect
* Removed unused function and provided Scaladoc for retrieveParent
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It was private and unused
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* Include and check when scoping as part of reg/mem/wire/node bindings
* Allow outdated 'when' behavior of CHIRRTL memory ports with enables
* Extend cross-module / when-visibility checks to all data refs
* Fixes #1512
* Cannot be checked if outside a module context
* E.g. delayed evaluation of printf / assert args
* Add basic test cases for cross-module refs / signals escaping when scopes
* Remove illegal cross-module references from existing tests
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* Added broken auto-clonetype test
* Added bugfix for 2.11
* Add descriptive comment for 2.11 special case
* Update src/test/scala/chiselTests/AutoClonetypeSpec.scala
* Update src/test/scala/chiselTests/AutoClonetypeSpec.scala
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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Added prefixing and a compiler plugin to improve naming. Only works for Scala 2.12 and above.
Co-authored-by: Jack Koenig <koenig@sifive.com>
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* Add `check(...)` affordance
* Add assert (renamed from check and fixed)
* Add verification statements
* Move formal to experimental.verification
* Make test use ChiselStage
`generateFirrtl` has been cut from Chisel
* Fix newly introduced style warnings
* Fix some old style warnings for good measure
* Revert "Fix some old style warnings for good measure"
This reverts commit 31d51726c2faa4c277230104bd469ff7ffefc890.
* Cut scalastyle comments
* Cut formal delimiter comments
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* Closes #1385
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Immediately throw Builder.error errors outside hardware context
* Add example of hidden no-hardware-context error from #1422
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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