diff options
| author | Jack Koenig | 2021-03-29 14:56:22 -0700 |
|---|---|---|
| committer | GitHub | 2021-03-29 21:56:22 +0000 |
| commit | 9c9bc131b031764332aeb2b175ae8abc500b8801 (patch) | |
| tree | 76ed77dedf603179cdfaa6a556dceee7b0a8fb19 /core | |
| parent | 7b8fbbe8913a2eb92f50948dc2be50dc482fb58d (diff) | |
Provide useful message on Vec.apply require (#1838)
Diffstat (limited to 'core')
| -rw-r--r-- | core/src/main/scala/chisel3/Aggregate.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/core/src/main/scala/chisel3/Aggregate.scala b/core/src/main/scala/chisel3/Aggregate.scala index c5a917fa..df992bb9 100644 --- a/core/src/main/scala/chisel3/Aggregate.scala +++ b/core/src/main/scala/chisel3/Aggregate.scala @@ -342,7 +342,7 @@ object VecInit extends SourceInfoDoc { // DummyImplicit or additional type parameter will break some code. // Check that types are homogeneous. Width mismatch for Elements is safe. - require(!elts.isEmpty) + require(elts.nonEmpty, "Vec hardware values are not allowed to be empty") elts.foreach(requireIsHardware(_, "vec element")) val vec = Wire(Vec(elts.length, cloneSupertype(elts, "Vec"))) |