diff options
| author | Megan Wachs | 2021-01-11 07:19:17 -0800 |
|---|---|---|
| committer | GitHub | 2021-01-11 15:19:17 +0000 |
| commit | b578aa5e45e4ac5c2a71dda42367863a577ccaa4 (patch) | |
| tree | 32667dac2e95d0e7ca719b60cca510bda9342cfc /core | |
| parent | 688c86ab209b4019455d278e37e4ad097489d1c5 (diff) | |
Make `toTarget` fail if called on a Literal (or would otherwise not serialize properly) (#1714)
* Add (failing) Test for Data toTarget calls
Add scaladoc and clean up test
* Builder: don't let .toTarget pass if it won't be able to deserialize properly later
* Update src/test/scala/chiselTests/ReferenceTargetSpec.scala
* Rename and simplify tests for literal toTarget
Diffstat (limited to 'core')
| -rw-r--r-- | core/src/main/scala/chisel3/internal/Builder.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/core/src/main/scala/chisel3/internal/Builder.scala b/core/src/main/scala/chisel3/internal/Builder.scala index 1c3a0005..b7772aea 100644 --- a/core/src/main/scala/chisel3/internal/Builder.scala +++ b/core/src/main/scala/chisel3/internal/Builder.scala @@ -9,6 +9,7 @@ import chisel3.experimental._ import chisel3.internal.firrtl._ import chisel3.internal.naming._ import _root_.firrtl.annotations.{CircuitName, ComponentName, IsMember, ModuleName, Named, ReferenceTarget} +import _root_.firrtl.annotations.AnnotationUtils.{validComponentName} import chisel3.internal.Builder.Prefix import logger.LazyLogging @@ -276,6 +277,7 @@ private[chisel3] trait NamedComponent extends HasId { */ final def toTarget: ReferenceTarget = { val name = this.instanceName + if (!validComponentName(name)) throwException(s"Illegal component name: $name (note: literals are illegal)") import _root_.firrtl.annotations.{Target, TargetToken} Target.toTargetTokens(name).toList match { case TargetToken.Ref(r) :: components => ReferenceTarget(this.circuitName, this.parentModName, Nil, r, components) |
