diff options
| -rw-r--r-- | core/src/main/scala/chisel3/internal/Builder.scala | 2 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/LiteralToTargetSpec.scala | 31 |
2 files changed, 33 insertions, 0 deletions
diff --git a/core/src/main/scala/chisel3/internal/Builder.scala b/core/src/main/scala/chisel3/internal/Builder.scala index 1c3a0005..b7772aea 100644 --- a/core/src/main/scala/chisel3/internal/Builder.scala +++ b/core/src/main/scala/chisel3/internal/Builder.scala @@ -9,6 +9,7 @@ import chisel3.experimental._ import chisel3.internal.firrtl._ import chisel3.internal.naming._ import _root_.firrtl.annotations.{CircuitName, ComponentName, IsMember, ModuleName, Named, ReferenceTarget} +import _root_.firrtl.annotations.AnnotationUtils.{validComponentName} import chisel3.internal.Builder.Prefix import logger.LazyLogging @@ -276,6 +277,7 @@ private[chisel3] trait NamedComponent extends HasId { */ final def toTarget: ReferenceTarget = { val name = this.instanceName + if (!validComponentName(name)) throwException(s"Illegal component name: $name (note: literals are illegal)") import _root_.firrtl.annotations.{Target, TargetToken} Target.toTargetTokens(name).toList match { case TargetToken.Ref(r) :: components => ReferenceTarget(this.circuitName, this.parentModName, Nil, r, components) diff --git a/src/test/scala/chiselTests/LiteralToTargetSpec.scala b/src/test/scala/chiselTests/LiteralToTargetSpec.scala new file mode 100644 index 00000000..3c404f2d --- /dev/null +++ b/src/test/scala/chiselTests/LiteralToTargetSpec.scala @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: Apache-2.0 + +package chiselTests + +import chisel3._ +import chisel3.stage.ChiselStage + +import org.scalatest._ +import org.scalatest.freespec.AnyFreeSpec +import org.scalatest.matchers.should.Matchers + + +class LiteralToTargetSpec extends AnyFreeSpec with Matchers { + + "Literal Data should fail to be converted to ReferenceTarget" in { + + the [chisel3.internal.ChiselException] thrownBy { + + class Bar extends RawModule { + val a = 1.U + } + + class Foo extends RawModule { + val bar = Module(new Bar) + bar.a.toTarget + } + + ChiselStage.elaborate(new Foo) + } should have message "Illegal component name: UInt<1>(\"h01\") (note: literals are illegal)" + } +} |
