chiselX - Chisel with SFC compatibility

Age	Commit message (Expand)	Author
2017-08-17	Use firrtl elses in elsewhen/otherwise case emission (#510)	Albert Magyar
2017-08-17	More of the bindings refactor (#635)	Richard Lin
2017-08-17	Make Reset a trait (#672)	Jack Koenig
2017-08-11	Rename userDir->specifiedDir (#671)	Richard Lin
2017-08-08	Give default direction to children of Vecs in compatibility code	Jack Koenig
2017-08-07	Don't assign default direction to Analog in Chisel._	Jack Koenig
2017-07-28	Black box top-level IO fix (#655)	Richard Lin
2017-07-27	Fix style of literal creators (#637)	Chick Markley
2017-07-25	Fixed point width inference was wrong when binary points didn't align. (#590)	Angie Wang
2017-06-26	Directions internals mega-refactor (#617)	Richard Lin
2017-05-31	Add dontTouch for annotating Data to not be removed	Jack Koenig
2017-05-12	Changed multiplication of SInt and UInt (#611)	Adam Izraelevitz
2017-05-10	Add implicit CompileOptions to Record and Bundle (#595)	Jack Koenig
2017-05-04	Connecting basic types wrong should error in chisel (#497)	Chick Markley
2017-05-03	Clear clock and reset scope for RawModule (#607)	Richard Lin
2017-04-26	Deprecate fromBits and clock/reset constructors (#583)	Richard Lin
2017-04-26	Dropimportnotstrict492 - More updates to get things through rocket-chip. (#592)	Jim Lawson
2017-04-25	Remove explicit import of NotStrict - fixes #492 (#494)	Jim Lawson
2017-04-21	Remove VecLike/IndexedSeq from Mem type (#589)	Richard Lin
2017-04-15	Fix assignment from 0-entry Vec: add test (#580)	Andrew Waterman
2017-04-13	Module Hierarchy Refactor (#469)	Richard Lin
2017-04-12	Fix one hot mux (#573)	Chick Markley
2017-04-04	Use input element to decide if Vec of values has direction (#570)	Jack Koenig
2017-04-04	Define CompileOptions case class to support CompileOptions manipulation. (#572)	Jim Lawson
2017-04-02	Make Module instantiations draw clock from Builder instead of parent (#568)	Jack Koenig
2017-03-28	Creating FixedPoint literals was throwing away width when specifically provided.	chick
2017-03-27	Support Vec(0) fields in Bundles, just like Option[Data]; add test	Andrew Waterman
2017-03-24	Fix getWidth on empty Vecs; add test	Andrew Waterman
2017-03-24	Fixed fix, allow Mux of different binary points and widths (#559)	Richard Lin
2017-03-13	Revert "Change Vec creation to check if gen is lit (and hence needs t… (#530)	Jim Lawson
2017-03-08	Deprecate old Reg with nulls constructor (#455)	Richard Lin
2017-02-27	Record: allow elements to start with a digit	Wesley W. Terpstra
2017-02-24	Fix mismatch between Chisel and Firrtl on UInt -& UInt	Jack Koenig
2017-02-24	Escape % in assertion messages	Jack Koenig
2017-02-23	Fend off future bug - replace FixedPoint ":=" with "connect". (#516)	Jim Lawson
2017-02-22	Bugfix #513. Fix BPSet width inference in Chisel3 (#523)	Adam Izraelevitz
2017-02-17	Builderreflectionfix (#515)	Angie Wang
2017-02-16	Add scaladoc examples for Vec and Bundle (#511)	Chick Markley
2017-02-16	Add support for clock and reset scoping (#509)	Jack Koenig
2017-02-15	Blackbox comments spelling correction thanks to edwardcwang	Fabien Marteau
2017-02-15	BlackBox documentation: adding the verilog template to generate	Fabien Marteau
2017-02-15	Adding a BlackBox example in code documentation	Fabien Marteau
2017-02-15	Implement asTypeOf, refactor internal APIs (#450)	Richard Lin
2017-02-15	Fixed point factory stuff (#505)	Chick Markley
2017-02-08	Add Analog type	Jack Koenig
2017-02-08	Add counter for depth of when scope	Jack Koenig
2017-02-07	Fix up Absolute value #abs (#491)	Chick Markley
2017-02-07	Add macro for compile options materialize to prevent its use in chisel core	ducky
2017-02-07	Rename SeqMem to SyncReadMem. (#490)	Jim Lawson
2017-02-03	Added vec IO tests for #104 (#480)	Jim Lawson