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2020-02-06Emit FIRRTL andr, orr for Bits.{andR, orR}Schuyler Eldridge
Change the emission strategy for Bits methods andR and orR to emit FIRRTL bitwise reduce operations andr and orr. Add two tests that assert the correct behavior of these operations in BitwiseOpsSpec. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-05Add information about widths to RegNext (#1318)Schuyler Eldridge
Adds additional Scaldoc to the RegNext object that (1) indicates that the width is not set and (2) shows an example of how to construct a RegNext-like construct with a set width. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-03Add read-under-write parameter to SyncReadMem (#1183)Albert Magyar
* Add support for readUnderWrite to SyncReadMem * Add write collision behavior test to MemorySpec * Update constant names
2020-01-31Merge branch 'master' into add-asbool-to-clockChick Markley
2020-01-25Fixed code example typo in comment (#1294)Leway Colin
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-01-25Remove redundancy code (#1296)Leway Colin
* Remove redundancy code * Remove blank line * BitPat supports whitespace and underscores, presumably for human readability. The BitPat.parse factory though did not remove these from the returned count. This fixes that adds whitespace and underscores to the unit tests This is an updated vesion of Chisel PR #1069 Co-authored-by: Chick Markley <chick@qrhino.com> Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-01-23Minor changes - update comments, use MaxBitsBigIntToBigDecimal instead of ↵Jim Lawson
'108'. (#1309) Co-authored-by: Chick Markley <chick@qrhino.com>
2020-01-22Update comment for Clock.asBool()Jim Lawson
2020-01-22Merge branch 'master' into add-asbool-to-clockChick Markley
2020-01-22Merge branch 'master' into big-decimal-methods-for-num-typesChick Markley
2020-01-22Change when/switch thunk type to Any (#1308)Schuyler Eldridge
* Change when thunks return type to Any Changes the type of the thunk for when and WhenContext methods from call-by-name Unit to call-by-name Any. This prevents a warning (-Ywarn-value-discard) where a when thunk is returning something other than Unit that is then discarded, e.g., another WhenContext. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Change switch thunk return to type to Any Changes the type of switch thunks from call-by-name Unit to call-by-name Any. This prevents a warning (-Ywarn-value-discard) when the internals of a switch block return something other than Unit which is then discarded. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-01-21Merge branch 'master' into big-decimal-methods-for-num-typeschick
# Conflicts: # src/test/scala/chiselTests/IntervalSpec.scala
2020-01-07Merge branch 'master' into add-asbool-to-clockJim Lawson
2020-01-07Remove over design (#1237)Leway Colin
Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Co-authored-by: Chick Markley <chick@qrhino.com>
2019-12-19Removed accidentally introduced parenschick
2019-12-18Add method asBool to Clock.chick
Shortcut for .asUInt.asBool Added test to show it works
2019-12-18- New trait HasBinaryPoint which provides literal values as double and big ↵chick
decimal - made .F and .I work for creating fixed point and interval lits from big decimal - Added NumObject trait which provides new math conversions - Made a Num object that extends NumObject - Add this trait to FixedPoint and Interval for backward compatibility - Removed code that is now in NumObject, keeping things DRY - Add tests to FixedPointSpec to show lit conversion to double and big decimal - Add tests to IntervalSpec to show lit conversion to double and big decimal - Add tests to LiteralExtractorSpec to show general math conversions between BigInts with binary points and double and big decimal
2019-12-17Merge branch 'master' into interval-fix-2Chick Markley
2019-12-17Band aid until litOption is implemented for Aggregates. (#1277)Jim Lawson
This is just a band aid until an Aggregate `isLit()` method (for which work has begun) is implemented.
2019-12-12Fixed problem creating Interval literals with full rangeschick
- boundary testing was not taking binary point into account correctly - add tests to show where things work and where they are supposed to fail
2019-12-11- Change getPossibleValues of Interval to return a NumericRange former Seq ↵chick
materialized all values - Fixed computation in getHighestPossibleValue, erroneously was using lower intead of upper
2019-12-04Add ChiselEnum to BundleLiterals (#1215)Zhuanhao Wu
2019-12-02Fix asTypeOf for Clock (#1258)Jack Koenig
2019-11-29Fix deprecation warning that leaks into user code (#1256)Jack Koenig
Data.isLit called Data.litArg which would trigger a Chisel runtime deprecation warning in user code with source locator Data.scala:488
2019-11-27Fix bidirectional Wire with Analog (#1252)Jack Koenig
2019-11-17Improve error message when assigning from Seq to Vec (#1239)Andrew Waterman
2019-11-15Enable @chiselName on non-module classes (#1209)John's Brew
2019-11-05Support literals cast to aggregates as async reset reg init values (#1225)Jack Koenig
Accomplished by changing the code gen for casting literals to aggregates. Rather than connecting the literal to a wire that is then bit selected from, just bit select from the literal which saves the creation of an intermediate wire and matches FIRRTL's semantics for legal async reset initial values.
2019-11-02Better anonymous and class-in-function desiredNameSchuyler Eldridge
This changes the desired name of a Module to provide non-numeric naming for anonymous Modules and Modules defined inside function bodies. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-10-18Interval Data Type Support for Chisel (#1210)Chick Markley
Plan to be released with 3.3. Breaks experimental Range API. Adds new Interval type and associated support. This commit adds the following: - Renamed Range to IntervalRange to avoid name collision with scala Range - Changed RangeTransform macro to Return an IntervalRange - Improved error messages on missing comma or decimal - Added notational support for binary point - Some formatting cleanup also - SIntFactory - Change to use IntervalRange API - UIntFactory - UInt from range has custom width computation - It does not need to deal with lowerbound extending bit requirements - Code to handle special case of range"[0,0]" to have a width of 1 - IR.scala - Removed Bound and other constraint code that was duplicating firrtl stuff - Added new RangeType - Added IntervalRange class and object - RangeSpec - modified just a bit to handle notational differences - previous range interpolator returned tuple now returns IntervalRange - Add IntervalType to emitter - Added IntervalSpec with many tests - Added ScalaIntervalSimulatorSpec which tests golden model for Interval - Added ScalaIntervalSimulator which is a golden model for Interval - This gold may not have been polished to a high sheen - Add IntervalLit cases to Converter - Add Interval PrimOps to IR - asInterval, wrap, squz, clip, setp, decp, incp - Add IntervalLit class to IR - Add Interval to MonoConnect - Add Interval Type to Bits (in experimental package) - add conversions to Interval from other types - Add Interval clone stuff to Data - Add Literal creation helpers to chisel3 package - these may move to experimental if I can figure that out
2019-10-08Fix direction of dynamic index in complex Vec (#1196)Jack Koenig
Dynamically indexing a Vec of Flipped bidirectional Bundles would get the wrong directions on the elements of the Bundles Fixes #1192
2019-10-07Improve desiredName for nested objects/classesSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-16Da steve101 tree reduce (#485)Jack Koenig
* Add a tree reduce function to Vec * Change function names of reduce operation function in Vec * Change reference to single layer operation in Vec.reduce * Commint name change for pair macro * Remove pair, call not necessary and can just be used from grouped(2) and map * Changed to reduceTree, added default identity function for single reduce. * Change style of Vec.reduceTree and tests to chisel3 and canonical Scala style * Cleanup Vec initialization, implicitCompileOptions
2019-09-11Move dontTouch, RawModule, and MultiIOModule out of experimental (#1162)Jim Lawson
* Move dontTouch out of experimental package. * Move RawModule, MultiIOModule out of experimental. * Respond to comments - Move LagacyModule from experimental to internal. *NOTE*: At some point, these module definitions (especially those in separate packages) should be moved to individual files at the appropriate location in the source tree. The current organization is purely to support comparison with prior versions. * Fix up a few more imports.
2019-08-28refactor out _Factory traits + address EOF WSKamyar Mohajerani
2019-08-28Refactor Element, Num, and Analog classes to their own files (no functional ↵Kamyar Mohajerani
changes)
2019-08-19Refactor: remove redundant code (#1152)Leway Colin
* Refactor: remove redundant code * Change to protected API * Remove type hierarchy
2019-08-13Add support for asynchronous reset (#1011)Jack Koenig
Adds new AsyncReset and "abstract" Reset types. Reset is inferred in FIRRTL to be either AsyncReset or Bool. The "reset type" of a register is set by the type of its reset signal: val asyncReset: AsyncReset = IO(Input(AsyncReset())) val syncReset: Bool = IO(Input(Bool())) val abstractReset: Reset = IO(Input(Reset())) val asyncReg = withReset(asyncReset) { RegInit(0.U) } val syncReg = withReset(syncReset) { RegInit(0.U) } val inferredReg = withReset(abstractReset) { RegInit(0.U) } AsyncReset can be cast to and from Bool. Whereas synchronous reset is equivalent to a mux in front of a flip-flop and thus can be driven by logic, asynchronous reset requires that the reset value is a constant. This is checked in FIRRTL. Inference of the concrete type of a Reset occurs based on the type the Reset's drivers. This inference is very simple, it is simple forward propagation of the type, but it allows for writing blocks and modules that are agnostic to the reset type. In particular, the implicit `reset` value in MultiIOModule and thus Module is now concretely an instance of Reset and thus will be inferred in FIRRTL.
2019-08-12Aspect-Oriented Programming for Chisel (#1077)Adam Izraelevitz
Added Aspects to Chisel, enabling a mechanism for dependency injection to hardware modules.
2019-08-08Require target is hardware for Vec.apply(a: UInt)Schuyler Eldridge
Adds a check that a Vec being indexed by a UInt is, in fact, a hardware type. This includes a test for this. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-01Flatten *FactoryBase hierarchySchuyler Eldridge
This renames all *FactoryBase traits to *Factory, removes transparent *Factory objects, and propagates this flattened hierarchy throughout the codebase. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-01Remove anything deprecated since before 3.2Schuyler Eldridge
Anything removed by this that is used by the compatibility layer is migrated to the compatibility layer. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Clarify Module deprecationsSchuyler Eldridge
This adds a clarification to the deprecation message for RawModule, MultiIOModule, UserModule, and ImplicitModule. While these were technically deprecated "since the beginning of time", this adds a comment that these aliases will be removed in 3.3. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Fix deprecation warningsSchuyler Eldridge
Change "since" specification from "chisel3.2" to "3.2". This aligns with usages in the rest of the codebase. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-30Change core deprecation "since" from 3.3 -> 3.2Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-24Fix Num.+ ScaladocSchuyler Eldridge
Change Num.+ Scaladoc to state that this is not a growing addition. Note that this is problematic either way as this macro is resolved to an abstract method. Classes implementing this typeclass are technically free to violate what we put in the Scaladoc here. h/t @kammoh Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-18Support Analog DontCare bulk-connect (#1056)Richard Lin
Short-term patch to enable this useful behavior. In the future, we may want to rearchitect the type system and/or rethink the more edge-case connect behavior.
2019-06-24Changed Value macro in ChiselEnum so that it doesn't use deprecated (#1104)Hasan Genc
function. This also fixes prior issue where ChiselEnums would not compile when @chiselName was applied to a module containing a ChiselEnum
2019-05-21Minor Scaladoc update (#1099)Jim Lawson
* Minor Scaladoc update - add/move package descriptive text - fix FixedPoint link (it's chisel3.experimental.FixedPoint) * Add missing period at EOS
2019-05-20Repackagecore rebase (#1078)Jim Lawson
* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3 and deal with the subsequent fallout. * Move Aggregate, Clock, Mem, Printf, Reg * Move almost all chisel3.core definitions to chisel3 or chisel3.experimental * Revive core package object to provide aliases for moved definitions. * Cleanup package definitions; eliminate ambiguous implicits * Move more definitions to experimental. Extract BaseModule, DataMirror, ExtModule, IO into their own files. * Put BitPat back in chisel3.util * More experimental motion - avoid multiple import definitions. * Add experimental.FixedPoint alias * Add EnumType definition to core package. Update deprecated messages to refer to correct object * Move FixedPoint into the experimental package (but keep it in Bits.scala). * Add missing implicits to core/package - compatibility * Cleanup: update ScalaDoc references; remove unused imports * Add Reset alias to core/package * Use common 3.2 version in deprecation warning * Move Binding from core to internal. * Optimize imports. * Repair IntelliJ's overly cleanliness. * Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3 and deal with the subsequent fallout. Move Aggregate, Clock, Mem, Printf, Reg Move almost all chisel3.core definitions to chisel3 or chisel3.experimental Revive core package object to provide aliases for moved definitions. Cleanup package definitions; eliminate ambiguous implicits Move more definitions to experimental. Extract BaseModule, DataMirror, ExtModule, IO into their own files. Add EnumType definition to core package. Update deprecated messages to refer to correct object Move FixedPoint into the experimental package (but keep it in Bits.scala). Add missing implicits to core/package - compatibility Cleanup: update ScalaDoc references; remove unused imports Use common 3.2 version in deprecation warning Move Binding from core to internal. * Change == to reference equality (eq) in Data print (#1044) * Remove @chiselName from MixedVec (#1045) * Fix enum annotations (#936) * Turned off strong enum annotations because they weren't working with Vec indexes * Add new EnumVecAnnotation for vecs of enums and vecs of bundles with enum fields * Changed Clock's width parameter back to a fixed constant value of 1 * Fixed enum annotations for Vecs of Bundles which contain enum elements * Fixed usage of "when/otherwise" to use consistent style * Add Record to type hierarchy documentation * Undeprecate isLit (#1048) * move doNotDedup to experimental (#1008) * Aggregate coverage - aggregate tests but not publishing (#1040) Discover a working combination of aggregate usage to enable coverage of subproject testing but publish a single Jar. Use "scalastyle-test-config.xml" for scalastyle config in tests. Enable "_" in method names and accept method names ending in "_=". Re-sync scalastyle-test-config.xml with scalastyle-config.xml This should finally fix #772. * Check field referential equality in autoclonetype (#1047) * Allow naming annotation to work outside builder context (#1051) * Try to eliminate JVM hang due to static initialization deadlock (#1053) * Make core.DontCare private to chisel3 (#1054) Force clients to access 'DontCare' through the chisel3 package to ensure it's created as a chisel3 object and not a client object. * Ignore empty aggregates elements when binding aggregate direction (#946) Previously, including an empty aggregate in a Bundle would cause a MixedDirectionAggregateException because it has no elements and thus doesn't have a direction * Add SampleElementBinding for Vec sample elements * Add ActualDirection.Empty for bound empty aggregates * Detect bundle aliasing (#1050) * Implement connectFromBits in ChiselEnum (#1052) This is necessary to use ChiselEnum in aggregates where things are casted using .asTypeOf * Optimize imports. * Move Analog to experimental. * More repackage cleanup - reduce differences with master. * Cleanup chisel3 references. * More chisel3 reference cleanup. * Merge cleanup. * Remove unused import * Bump core deprecation to 3.3 * Move DontCare back into Data.scala inside package internal * Re-indent experimental/internal package code * Move code back to original files - facilitate comparison with other branches * Some code motion, update imports, minimize master differences Move exceptions up to chisel3 package object - they're part of the interface. * More master diff minimization. * Try to eliminate JVM hang due to static initialization deadlock (#1053) * Ignore empty aggregates elements when binding aggregate direction (#946) Previously, including an empty aggregate in a Bundle would cause a MixedDirectionAggregateException because it has no elements and thus doesn't have a direction * Add SampleElementBinding for Vec sample elements * Add ActualDirection.Empty for bound empty aggregates * Implement connectFromBits in ChiselEnum (#1052) This is necessary to use ChiselEnum in aggregates where things are casted using .asTypeOf * Move Analog to experimental. More repackage cleanup - reduce differences with master. Cleanup chisel3 references. More chisel3 reference cleanup. * Fix wrong directionality for Vec(Flipped()) Create Chisel IR Port() in a way that Converter is happy with. Also add more extensive test suite for future-proofing. Close #1063 * Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3 and deal with the subsequent fallout. Move Aggregate, Clock, Mem, Printf, Reg Move almost all chisel3.core definitions to chisel3 or chisel3.experimental Revive core package object to provide aliases for moved definitions. Cleanup package definitions; eliminate ambiguous implicits Move more definitions to experimental. Extract BaseModule, DataMirror, ExtModule, IO into their own files. Put BitPat back in chisel3.util More experimental motion - avoid multiple import definitions. Add experimental.FixedPoint alias Add EnumType definition to core package. Update deprecated messages to refer to correct object Move FixedPoint into the experimental package (but keep it in Bits.scala). Add missing implicits to core/package - compatibility Cleanup: update ScalaDoc references; remove unused imports Add Reset alias to core/package Use common 3.2 version in deprecation warning Move Binding from core to internal. Optimize imports. Repair IntelliJ's overly cleanliness. Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3 and deal with the subsequent fallout. Move Aggregate, Clock, Mem, Printf, Reg Move almost all chisel3.core definitions to chisel3 or chisel3.experimental Revive core package object to provide aliases for moved definitions. Cleanup package definitions; eliminate ambiguous implicits Move more definitions to experimental. Extract BaseModule, DataMirror, ExtModule, IO into their own files. Add EnumType definition to core package. Update deprecated messages to refer to correct object Move FixedPoint into the experimental package (but keep it in Bits.scala). Add missing implicits to core/package - compatibility Cleanup: update ScalaDoc references; remove unused imports Use common 3.2 version in deprecation warning Move Binding from core to internal. Optimize imports. Merge cleanup. Remove unused import Bump core deprecation to 3.3 Move DontCare back into Data.scala inside package internal Re-indent experimental/internal package code Move code back to original files - facilitate comparison with other branches Some code motion, update imports, minimize master differences Move exceptions up to chisel3 package object - they're part of the interface. More master diff minimization. Fix minor discrepancies with repackagecore-testbed * Remove redundant imports As part of its import updating process, IntelliJ converted some import statements to `import package.{object, _}`. Is this intended to show an explicit dependency on `package.object` and a further dependency on `package` implicits? Unsure. Replace these with `import package._` * Move the BaseModule object into the internal package.
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