diff options
| author | Leway Colin | 2020-01-25 09:16:43 +0800 |
|---|---|---|
| committer | mergify[bot] | 2020-01-25 01:16:43 +0000 |
| commit | 160e019e38c933112836cccbb38c5f397427cf7f (patch) | |
| tree | bb59295675b2002e9a5ef53718b977de56e20dea /chiselFrontend/src | |
| parent | 37e2b8fee3c9d583fa9d023637e8bc327dc9866f (diff) | |
Remove redundancy code (#1296)
* Remove redundancy code
* Remove blank line
* BitPat supports whitespace and underscores, presumably for human readability.
The BitPat.parse factory though did not remove these from the returned count.
This fixes that adds whitespace and underscores to the unit tests
This is an updated vesion of Chisel PR #1069
Co-authored-by: Chick Markley <chick@qrhino.com>
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'chiselFrontend/src')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/RawModule.scala | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/RawModule.scala b/chiselFrontend/src/main/scala/chisel3/RawModule.scala index 4155ef4a..2b184a50 100644 --- a/chiselFrontend/src/main/scala/chisel3/RawModule.scala +++ b/chiselFrontend/src/main/scala/chisel3/RawModule.scala @@ -184,17 +184,6 @@ package internal { // Allow access to bindings from the compatibility package protected def _compatIoPortBound() = portsContains(io)// scalastyle:ignore method.name - protected override def nameIds(rootClass: Class[_]): HashMap[HasId, String] = { - val names = super.nameIds(rootClass) - - // Allow IO naming without reflection - names.put(io, "io") - names.put(clock, "clock") - names.put(reset, "reset") - - names - } - private[chisel3] override def namePorts(names: HashMap[HasId, String]): Unit = { for (port <- getModulePorts) { // This should already have been caught |