Removed accidentally introduced parens

1 files changed, 1 insertions, 1 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/Clock.scala b/chiselFrontend/src/main/scala/chisel3/Clock.scala
index 1aadf167..aad515e4 100644
--- a/chiselFrontend/src/main/scala/chisel3/Clock.scala
+++ b/chiselFrontend/src/main/scala/chisel3/Clock.scala
@@ -38,6 +38,6 @@ sealed class Clock(private[chisel3] val width: Width = Width(1)) extends Element
   override def do_asUInt(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): UInt = pushOp(DefPrim(sourceInfo, UInt(this.width), AsUIntOp, ref)) // scalastyle:ignore line.size.limit
   private[chisel3] override def connectFromBits(that: Bits)(implicit sourceInfo: SourceInfo,
       compileOptions: CompileOptions): Unit = {
-    this := that.asBool().asClock
+    this := that.asBool.asClock
   }
 }