From 2224274cc5a42caa1e74b45573b4c7c09c85d227 Mon Sep 17 00:00:00 2001
From: chick
Date: Thu, 19 Dec 2019 09:39:52 -0800
Subject: Removed accidentally introduced parens

---
 chiselFrontend/src/main/scala/chisel3/Clock.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'chiselFrontend/src')

diff --git a/chiselFrontend/src/main/scala/chisel3/Clock.scala b/chiselFrontend/src/main/scala/chisel3/Clock.scala
index 1aadf167..aad515e4 100644
--- a/chiselFrontend/src/main/scala/chisel3/Clock.scala
+++ b/chiselFrontend/src/main/scala/chisel3/Clock.scala
@@ -38,6 +38,6 @@ sealed class Clock(private[chisel3] val width: Width = Width(1)) extends Element
   override def do_asUInt(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): UInt = pushOp(DefPrim(sourceInfo, UInt(this.width), AsUIntOp, ref)) // scalastyle:ignore line.size.limit
   private[chisel3] override def connectFromBits(that: Bits)(implicit sourceInfo: SourceInfo,
       compileOptions: CompileOptions): Unit = {
-    this := that.asBool().asClock
+    this := that.asBool.asClock
   }
 }
-- 
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