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2016-09-07Fix bug in Printable FullName of submodule portjackkoenig
Printable was using HasId.instanceName to get full names of Chisel nodes. instanceName uses the parent module of the HasId to get the Component to use in calling fullName on the underlying Ref. Unfortunately this means that any reference to a port of a instance will leave off the instance name. Fixing this required the following: - Add Component argument to Printable.unpack so that we can call Arg.fullName directly in the Printable - Pass the currently emitting module as the Component to Printable.unpack in the Emitter - Remove ability to create FullName Printables from Modules since the Module name is not known until after the printf is already emitted This commit also updates the PrintableSpec test to check that FullName and Decimal printing work on ports of instances
2016-09-07Add Printable (#270)Jack Koenig
Printable is a new type that changes how printing of Chisel types is represented It uses an ordered collection rather than a format string and specifiers Features: - Custom String Interpolator for Scala-like printf - String-like manipulation of "hardware strings" for custom pretty-printing - Default pretty-printing for Chisel data types
2016-09-02Add/cleanup UInt/SInt factory methods.Jim Lawson
2016-09-02Deprecate asBits; modify deprecation warnings accordinglyAndrew Waterman
2016-09-01Remove O(n^2) code in Vec.apply(Seq)Andrew Waterman
The O(n) type legality check was redundantly executed n times. D'oh.
2016-09-01Deprecate Vec.fill() offering Vec(Seq.fill()).Jim Lawson
2016-09-01Move connection implicits from Module constructor to connection methods.Jim Lawson
Eliminate builder compileOptions.
2016-08-31Check that Vecs have homogeneous typesAndrew Waterman
Vec[Element] can have heterogeneous widths. Vec[Aggregate] cannot (but possibly could relax this by stripping widths from constituent Elements and relying on width inference).
2016-08-30Merge branch 'master' into gsdtJim Lawson
2016-08-30Use correct case for Strict/NotStrict compile options.Jim Lawson
2016-08-29Check module-specific compile options.Jim Lawson
Import chisel3.NotStrict.CompileOptions in Chisel package. Add CompileOptions tests.
2016-08-29Rename CompileOptions implicit objects.Jim Lawson
2016-08-29Pass compileOptions as an implicit Module parameter.Jim Lawson
2016-08-29Rename individual compile options.Jim Lawson
Stricter values are "true". Current default (not strict) values are "false".
2016-08-25Use bulkConnect in Vec,fill if any (flattened) element of the Vec has a ↵Jim Lawson
direction associated with it. This impetus for this came out of discussion during the chisel meeting of 8/24/16 in response to errors running the chisel tutorial examples Adder test.
2016-08-24Per Chisel meeting.chick
signalName -> instanceName SignalId -> InstanceId Based on Stephen's comments on PR
2016-08-23Swap name of compileOption "assumeNoDirectionIsOutput" to ↵Jim Lawson
"assumeNoDirectionIsInput".
2016-08-21provides signal name methods for firrtl annotation and chisel testersDonggyu Kim
* signalName: returns the chirrtl name of the signal * pathName: returns the full path name of the signal from the top module * parentPathName: returns the full path of the signal's parent module instance from the top module * parentModName: returns the signal's parent **module(not instance)** name.
2016-08-19Restore immutability of direction overrides.Jim Lawson
Input, Output, and Flipped clone their inputs.
2016-08-19Simplify autioIOWrap code in computePorts().Jim Lawson
As a side-effect, handle BlackBoxes correctly.
2016-08-18Add assumeNoDirectionIsOutput.Jim Lawson
2016-08-18Use isFirrtlFlipped() to determine port direction.Jim Lawson
2016-08-18Merge branch 'sdtwigg_connectwrap_renamechisel3' into gsdt_testsJim Lawson
Revive support for firrtl flip direction. Remove compileOptions.internalConnectionToInputOk
2016-08-17Rocket-chip updates.Jim Lawson
Assume LHSItOutput if neither side is driving. Restore Wire()'s removal of direction in binding.
2016-08-17Reduce rocket-chip elaboration errors.Jim Lawson
2016-08-16Add component to signature.Jim Lawson
2016-08-16Provide public SignalID trait to be used to conjure up a signal identifier.Jim Lawson
2016-08-16Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-08-15Make "def width" a private API; expose isWidthKnown instead (#257)Andrew Waterman
* Make "def width" a private API; expose isWidthKnown instead Resolves #256. Since width was used to determine whether getWidth would succeed, I added def isWidthKnown: Boolean but another option would be to expose something like def widthOption: Option[Int] ...thoughts? * Document getWidth/isWidthKnown * Add widthOption for more idiomatic Scala manipulation of widths
2016-08-12Use compileOptions to determine if Missing...FieldExceptions are thrown.Jim Lawson
2016-08-12Merge branch 'compile_options' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-08-12Add support for per-Module compilation options.Jim Lawson
Nothing uses these now, but when we integrate Stephen's PR200, we'll need a way to selectively enable some strict connection checks on a file by file basis. We plan to do this using package imports which will define suitable compilation options.
2016-08-11Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-08-09Support Module name overrides with "override def desiredName"Andrew Waterman
The API allowed this before, but not safely, as users could create name conflicts. This exposes the pre-deduplication/sanitization naming API, and closes the other one.
2016-08-09Legalize identifier names before printingAndrew Waterman
It's not entirely clear what the FIRRTL implementation supports, so I'm using the ANSI C requirements for the time being.
2016-08-04Deal with directions on Clocks.Jim Lawson
2016-08-03Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-07-31Expose asUInt from DataAndrew Waterman
Deprecating toBits removes the capability to cast an arbitrary type to UInt. While it's still possible to do so using asBits.asUInt, this creates boilerplate. (asBits is almost never useful itself.)
2016-07-31Fix two deprecation warningsAndrew Waterman
2016-07-28Add missing factory constructors.Jim Lawson
2016-07-27Additional compatibility code.Jim Lawson
2016-07-25Enable current (chisel2-style) compatibility mode.Jim Lawson
2016-07-25Minimize differences with master.Jim Lawson
Remove .Lit(x) usage. Undo "private" scope change. Change "firing" back to "fire". Add package level NODIR definition.
2016-07-25Merge branch 'master' into sdtwigg_connectwrap_renamechisel3Jim Lawson
2016-07-21Introduce chiselCloneType to distinguish from cloneType.Jim Lawson
Still fails one test - DirectionSpec in Direction.scala
2016-07-20More literal/width rangling.Jim Lawson
2016-07-20Distinguish between ?Int.Lit and ?Int.widthJim Lawson
2016-07-20Generate better names for nodes (#190)Jack Koenig
For Chisel nodes defined in Module class-level values of type Option or Iterable, we can still use reflection to assign names based on the name of the value. This works for arbitrary nesting of Option and Iterable so long as the innermost type is HasId. Note that this excludes Maps which always have an innermost type of Tuple2[_,_].
2016-07-20Compile ok.Jim Lawson
Need to convert UInt(x) into UInt.Lit(x) or UInt.width(x)
2016-07-19Fixes for only connectwrap version.Jim Lawson