| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-08-30 | Merge branch 'master' into gsdt | Jim Lawson | |
| 2016-08-30 | Use correct case for Strict/NotStrict compile options. | Jim Lawson | |
| 2016-08-29 | Check module-specific compile options. | Jim Lawson | |
| Import chisel3.NotStrict.CompileOptions in Chisel package. Add CompileOptions tests. | |||
| 2016-08-29 | Rename CompileOptions implicit objects. | Jim Lawson | |
| 2016-08-29 | Pass compileOptions as an implicit Module parameter. | Jim Lawson | |
| 2016-08-29 | Rename individual compile options. | Jim Lawson | |
| Stricter values are "true". Current default (not strict) values are "false". | |||
| 2016-08-25 | Use bulkConnect in Vec,fill if any (flattened) element of the Vec has a ↵ | Jim Lawson | |
| direction associated with it. This impetus for this came out of discussion during the chisel meeting of 8/24/16 in response to errors running the chisel tutorial examples Adder test. | |||
| 2016-08-24 | Per Chisel meeting. | chick | |
| signalName -> instanceName SignalId -> InstanceId Based on Stephen's comments on PR | |||
| 2016-08-23 | Swap name of compileOption "assumeNoDirectionIsOutput" to ↵ | Jim Lawson | |
| "assumeNoDirectionIsInput". | |||
| 2016-08-21 | provides signal name methods for firrtl annotation and chisel testers | Donggyu Kim | |
| * signalName: returns the chirrtl name of the signal * pathName: returns the full path name of the signal from the top module * parentPathName: returns the full path of the signal's parent module instance from the top module * parentModName: returns the signal's parent **module(not instance)** name. | |||
| 2016-08-19 | Restore immutability of direction overrides. | Jim Lawson | |
| Input, Output, and Flipped clone their inputs. | |||
| 2016-08-19 | Simplify autioIOWrap code in computePorts(). | Jim Lawson | |
| As a side-effect, handle BlackBoxes correctly. | |||
| 2016-08-18 | Add assumeNoDirectionIsOutput. | Jim Lawson | |
| 2016-08-18 | Use isFirrtlFlipped() to determine port direction. | Jim Lawson | |
| 2016-08-18 | Merge branch 'sdtwigg_connectwrap_renamechisel3' into gsdt_tests | Jim Lawson | |
| Revive support for firrtl flip direction. Remove compileOptions.internalConnectionToInputOk | |||
| 2016-08-17 | Rocket-chip updates. | Jim Lawson | |
| Assume LHSItOutput if neither side is driving. Restore Wire()'s removal of direction in binding. | |||
| 2016-08-17 | Reduce rocket-chip elaboration errors. | Jim Lawson | |
| 2016-08-16 | Add component to signature. | Jim Lawson | |
| 2016-08-16 | Provide public SignalID trait to be used to conjure up a signal identifier. | Jim Lawson | |
| 2016-08-16 | Merge branch 'master' into sdtwigg_connectwrap_renamechisel3 | Jim Lawson | |
| 2016-08-15 | Make "def width" a private API; expose isWidthKnown instead (#257) | Andrew Waterman | |
| * Make "def width" a private API; expose isWidthKnown instead Resolves #256. Since width was used to determine whether getWidth would succeed, I added def isWidthKnown: Boolean but another option would be to expose something like def widthOption: Option[Int] ...thoughts? * Document getWidth/isWidthKnown * Add widthOption for more idiomatic Scala manipulation of widths | |||
| 2016-08-12 | Use compileOptions to determine if Missing...FieldExceptions are thrown. | Jim Lawson | |
| 2016-08-12 | Merge branch 'compile_options' into sdtwigg_connectwrap_renamechisel3 | Jim Lawson | |
| 2016-08-12 | Add support for per-Module compilation options. | Jim Lawson | |
| Nothing uses these now, but when we integrate Stephen's PR200, we'll need a way to selectively enable some strict connection checks on a file by file basis. We plan to do this using package imports which will define suitable compilation options. | |||
| 2016-08-11 | Merge branch 'master' into sdtwigg_connectwrap_renamechisel3 | Jim Lawson | |
| 2016-08-09 | Support Module name overrides with "override def desiredName" | Andrew Waterman | |
| The API allowed this before, but not safely, as users could create name conflicts. This exposes the pre-deduplication/sanitization naming API, and closes the other one. | |||
| 2016-08-09 | Legalize identifier names before printing | Andrew Waterman | |
| It's not entirely clear what the FIRRTL implementation supports, so I'm using the ANSI C requirements for the time being. | |||
| 2016-08-04 | Deal with directions on Clocks. | Jim Lawson | |
| 2016-08-03 | Merge branch 'master' into sdtwigg_connectwrap_renamechisel3 | Jim Lawson | |
| 2016-07-31 | Expose asUInt from Data | Andrew Waterman | |
| Deprecating toBits removes the capability to cast an arbitrary type to UInt. While it's still possible to do so using asBits.asUInt, this creates boilerplate. (asBits is almost never useful itself.) | |||
| 2016-07-31 | Fix two deprecation warnings | Andrew Waterman | |
| 2016-07-28 | Add missing factory constructors. | Jim Lawson | |
| 2016-07-27 | Additional compatibility code. | Jim Lawson | |
| 2016-07-25 | Enable current (chisel2-style) compatibility mode. | Jim Lawson | |
| 2016-07-25 | Minimize differences with master. | Jim Lawson | |
| Remove .Lit(x) usage. Undo "private" scope change. Change "firing" back to "fire". Add package level NODIR definition. | |||
| 2016-07-25 | Merge branch 'master' into sdtwigg_connectwrap_renamechisel3 | Jim Lawson | |
| 2016-07-21 | Introduce chiselCloneType to distinguish from cloneType. | Jim Lawson | |
| Still fails one test - DirectionSpec in Direction.scala | |||
| 2016-07-20 | More literal/width rangling. | Jim Lawson | |
| 2016-07-20 | Distinguish between ?Int.Lit and ?Int.width | Jim Lawson | |
| 2016-07-20 | Generate better names for nodes (#190) | Jack Koenig | |
| For Chisel nodes defined in Module class-level values of type Option or Iterable, we can still use reflection to assign names based on the name of the value. This works for arbitrary nesting of Option and Iterable so long as the innermost type is HasId. Note that this excludes Maps which always have an innermost type of Tuple2[_,_]. | |||
| 2016-07-20 | Compile ok. | Jim Lawson | |
| Need to convert UInt(x) into UInt.Lit(x) or UInt.width(x) | |||
| 2016-07-19 | Fixes for only connectwrap version. | Jim Lawson | |
| 2016-07-19 | Merge in "complete" versions of Mem, Reg. | Jim Lawson | |
| 2016-07-19 | Fix LitBinding and MultiAssign tests. | Jim Lawson | |
| 2016-07-19 | Remove explicit literal binding. | Jim Lawson | |
| 2016-07-19 | Incorporate connection logic. | Jim Lawson | |
| Compiles but fails tests. | |||
| 2016-07-19 | Merge branch 'sdtwigg_rebase_renamechisel3' into sdtwigg_wrap_renamechisel3 | Jim Lawson | |
| 2016-07-18 | Update Chisel -> chisel3 references. | Jim Lawson | |
| 2016-07-18 | Rename "Chisel" to "chisel3" (only git mv). | Jim Lawson | |
| 2016-07-15 | Improve PopCount implementation | Andrew Waterman | |
| Clean up Scala code, and use +& to generate a lot less FIRRTL | |||
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