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2019-07-31Add Wire deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add Data deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add debug deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add Mem/SeqMem deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add LFSR16 deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add Queue deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add Enum deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Add BitPat deprecated compatibility testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-31Merge pull request #1142 from freechipsproject/enable-dummy-compatibility-testSchuyler Eldridge
Fixup and enable Dummy CompatibilitySpec test
2019-07-31Fixup and enable Dummy CompatibilitySpec testSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-01Fix shift register in READMEAdam Izraelevitz
2019-07-30Merge pull request #1138 from freechipsproject/core-deprecate-3.2Schuyler Eldridge
Core deprecation "since" should be "3.2" not "3.3"
2019-07-30Change core deprecation "since" from 3.3 -> 3.2Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-24Merge pull request #1129 from freechipsproject/num-maxwidthSchuyler Eldridge
Fix Num.+ Scaladoc
2019-07-24Fix Num.+ ScaladocSchuyler Eldridge
Change Num.+ Scaladoc to state that this is not a growing addition. Note that this is problematic either way as this macro is resolved to an abstract method. Classes implementing this typeclass are technically free to violate what we put in the Scaladoc here. h/t @kammoh Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-18Support Analog DontCare bulk-connect (#1056)Richard Lin
Short-term patch to enable this useful behavior. In the future, we may want to rearchitect the type system and/or rethink the more edge-case connect behavior.
2019-07-18Add width utility functions to avoid incorrect usage of bare log2Ceil(). (#819)Jim Lawson
* Add width utility functions to avoid incorrect usage of bare log2Ceil(). * Respond to comments: Remove apply(Data) method. Change name(s) to signedBitLength, unsignedBitLength. * Respond to comments - don't be lazy. Independently calculate the bit length to verify correct operation. * Respond to comments - return in.bitLength - 0 (not 1) for 0 * Respond to comments - update wdith for signed 0; add explicit tests. * Add comment expressing zero width wire assumption.
2019-07-16Fix typo in README.md (#1123)Henry Cook
2019-06-26Use Verilator 4.016 (#1116)Jim Lawson
* Use Verilator 4.016 Now that ucbbar/chisel3-tools has Verilator 4.016, use that for tests. * Update Verilator version in SETUP
2019-06-24Changed Value macro in ChiselEnum so that it doesn't use deprecated (#1104)Hasan Genc
function. This also fixes prior issue where ChiselEnums would not compile when @chiselName was applied to a module containing a ChiselEnum
2019-06-19First crack at updating the readme (#1106)Chick Markley
* First crack at updating the readme Goals Include up front example Simplify Get users to things quicker Move complicated details to wiki. * headers were not working, intellij and github don't use same render for .md files * Fix verb agreement * Add a fir filter diagram Compact the fir-filter code a bit * More compact filter * Additional README.md updates Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Don't use chisel-lang.org, drop HCL Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Fix link to fir image, make it relative * Proposed readme changes * Resize picture, restyle doc bullets
2019-06-11Added documentation to Decoupled, Conditionals, Counter (#1015)Adam Izraelevitz
* Added documentation to Decoupled, Conditionals, Counter * Fixed private Counter class error * Move Counter class deprecation and re-definition into util package object. * Revert "Move Counter class deprecation and re-definition into util package object." This reverts commit f61bdddf7051522363e1d203fcd46b512047c87d. * Restore the old Counter definition and address this in a separate PR. We can move the deprecation warning and the type definition into the util package object (see f61bdddf7051522363e1d203fcd46b512047c87d), but then we fail tests using Counter with a `ScalaReflectionException` in Aggregate.scala:779 (in def cloneType) when: `Some(mirror.reflect(this).symbol)` generates `type Counter is not a class`. * Made @ducky64 change to Counter doc Used to generate an inline (logic directly in the containing Module, no internal Module is created) hardware counter.
2019-06-03Merge pull request #1004 from freechipsproject/chisel-stageChick Markley
Chisel stage
2019-05-22Make Driver a ChiselStage compatibility layerSchuyler Eldridge
This converts the original chisel3.Driver to use chisel3.stage.ChiselStage. This is implemented in the following way: 1. ExecutionOptions are converted to an AnnotationSeq 2. The AnnotationSeq is preprocessed using phases contained in the Chisel DriverCompatibility objects. One of these *disables* the execution of FirrtlStage by ChiselStage. 3. ChiselStage runs on the preprocessed AnnotationSeq 4. The input ExecutionOptionsManager is mutated based on the output of ChiselStage. 5. The FIRRTL stage is re-enabled if it's supposed to run and selected FIRRTL DriverCompatibility phases run. 6. FirrtlStage runs 7. The output AnnotationSeq is "viewed" as a ChiselExecutionResult This modifies the original DriverSpec to make it more verbose with the addition of info statements. The functionality of the DriverSpec is unmodified. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add toAnnotations method to ChiselExecutionOptionsSchuyler Eldridge
Adds a method to enable conversion from ChiselExecutionOptions back to an AnnotationSeq. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add Driver Compatibility LayerSchuyler Eldridge
This includes phases necessary to provide backwards compatibility with the old Chisel3 Driver. These are placed in a DriverCompatibility object inside chisel3.stage.phases. The following four phases are included: - AddImplicitOutputFile (from a TopNameAnnotation) - AddImplicitOutputAnnotationFile phase - DisableFirrtlStage (to disable ChiselStage running FirrtlStage) - MutateOptionsManager (to update options after ChiselStage) - ReEnableFirrtlStage (to renable FirrtlStage if needed) Additionally, this adds a view of a ChiselExecutionResult for providing the legacy return type of the Chisel Driver. Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.ChiselStageSchuyler Eldridge
This adds ChiselStage, a reimplementation of chisel3.Driver as a firrtl.options.Stage. This is simplistically described as a pipeline of Phases. Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.phases.MaybeFirrtlStageSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2019-05-22Add stage.phases.AddImplicitOutputAnnotationFileSchuyler Eldridge
Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel.stage.phases.AddImplicitOutputFileSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.phases.Emitter PhaseSchuyler Eldridge
This adds an Emitter Phase that writes a ChiselCircuitAnnotation to a file if a ChiselOutputFileAnnotation is present. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.phases.Convert PhaseSchuyler Eldridge
This coalesces three distinct operations into one Convert Phase: 1. Chisel Circuit to FIRRTL Circuit (CHIRRTL) conversion 2. Conversion of Chisel Annotations to FIRRTL Annotations 3. Generation of RunFirrtlTransformAnnotations Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.phases.Elaborate PhaseSchuyler Eldridge
This adds an Elaborate Phase that expands ChiselGeneratorAnnotations into ChiselCircuitAnnotations and deletes the original. Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.phases.Checks PhaseSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add ChiselOptionsViewSchuyler Eldridge
Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.ChiselOptionsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage.ChiselCliSchuyler Eldridge
Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-22Add chisel3.stage AnnotationsSchuyler Eldridge
This adds the following FIRRTL Annotations to Chisel: - NoRunFirrtlCompilerAnnotation - PrintFullStackTraceAnnotation - ChiselGeneratorAnnotation - ChiselCircuitAnnotation - ChiselOutputFileAnnotation This includes tests for ChiselGeneratorAnnotation as this Annotation is able to be constructed from a String and to elaborate itself. Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-Authored-By: chick <chick@qrhino.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-21Include snapshots by default in mill (#1096)edwardcwang
* Include snapshots by default in mill. * Move repositories definition so all modules may use it.
2019-05-21Minor Scaladoc update (#1099)Jim Lawson
* Minor Scaladoc update - add/move package descriptive text - fix FixedPoint link (it's chisel3.experimental.FixedPoint) * Add missing period at EOS
2019-05-20Repackagecore rebase (#1078)Jim Lawson
* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3 and deal with the subsequent fallout. * Move Aggregate, Clock, Mem, Printf, Reg * Move almost all chisel3.core definitions to chisel3 or chisel3.experimental * Revive core package object to provide aliases for moved definitions. * Cleanup package definitions; eliminate ambiguous implicits * Move more definitions to experimental. Extract BaseModule, DataMirror, ExtModule, IO into their own files. * Put BitPat back in chisel3.util * More experimental motion - avoid multiple import definitions. * Add experimental.FixedPoint alias * Add EnumType definition to core package. Update deprecated messages to refer to correct object * Move FixedPoint into the experimental package (but keep it in Bits.scala). * Add missing implicits to core/package - compatibility * Cleanup: update ScalaDoc references; remove unused imports * Add Reset alias to core/package * Use common 3.2 version in deprecation warning * Move Binding from core to internal. * Optimize imports. * Repair IntelliJ's overly cleanliness. * Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3 and deal with the subsequent fallout. Move Aggregate, Clock, Mem, Printf, Reg Move almost all chisel3.core definitions to chisel3 or chisel3.experimental Revive core package object to provide aliases for moved definitions. Cleanup package definitions; eliminate ambiguous implicits Move more definitions to experimental. Extract BaseModule, DataMirror, ExtModule, IO into their own files. Add EnumType definition to core package. Update deprecated messages to refer to correct object Move FixedPoint into the experimental package (but keep it in Bits.scala). Add missing implicits to core/package - compatibility Cleanup: update ScalaDoc references; remove unused imports Use common 3.2 version in deprecation warning Move Binding from core to internal. * Change == to reference equality (eq) in Data print (#1044) * Remove @chiselName from MixedVec (#1045) * Fix enum annotations (#936) * Turned off strong enum annotations because they weren't working with Vec indexes * Add new EnumVecAnnotation for vecs of enums and vecs of bundles with enum fields * Changed Clock's width parameter back to a fixed constant value of 1 * Fixed enum annotations for Vecs of Bundles which contain enum elements * Fixed usage of "when/otherwise" to use consistent style * Add Record to type hierarchy documentation * Undeprecate isLit (#1048) * move doNotDedup to experimental (#1008) * Aggregate coverage - aggregate tests but not publishing (#1040) Discover a working combination of aggregate usage to enable coverage of subproject testing but publish a single Jar. Use "scalastyle-test-config.xml" for scalastyle config in tests. Enable "_" in method names and accept method names ending in "_=". Re-sync scalastyle-test-config.xml with scalastyle-config.xml This should finally fix #772. * Check field referential equality in autoclonetype (#1047) * Allow naming annotation to work outside builder context (#1051) * Try to eliminate JVM hang due to static initialization deadlock (#1053) * Make core.DontCare private to chisel3 (#1054) Force clients to access 'DontCare' through the chisel3 package to ensure it's created as a chisel3 object and not a client object. * Ignore empty aggregates elements when binding aggregate direction (#946) Previously, including an empty aggregate in a Bundle would cause a MixedDirectionAggregateException because it has no elements and thus doesn't have a direction * Add SampleElementBinding for Vec sample elements * Add ActualDirection.Empty for bound empty aggregates * Detect bundle aliasing (#1050) * Implement connectFromBits in ChiselEnum (#1052) This is necessary to use ChiselEnum in aggregates where things are casted using .asTypeOf * Optimize imports. * Move Analog to experimental. * More repackage cleanup - reduce differences with master. * Cleanup chisel3 references. * More chisel3 reference cleanup. * Merge cleanup. * Remove unused import * Bump core deprecation to 3.3 * Move DontCare back into Data.scala inside package internal * Re-indent experimental/internal package code * Move code back to original files - facilitate comparison with other branches * Some code motion, update imports, minimize master differences Move exceptions up to chisel3 package object - they're part of the interface. * More master diff minimization. * Try to eliminate JVM hang due to static initialization deadlock (#1053) * Ignore empty aggregates elements when binding aggregate direction (#946) Previously, including an empty aggregate in a Bundle would cause a MixedDirectionAggregateException because it has no elements and thus doesn't have a direction * Add SampleElementBinding for Vec sample elements * Add ActualDirection.Empty for bound empty aggregates * Implement connectFromBits in ChiselEnum (#1052) This is necessary to use ChiselEnum in aggregates where things are casted using .asTypeOf * Move Analog to experimental. More repackage cleanup - reduce differences with master. Cleanup chisel3 references. More chisel3 reference cleanup. * Fix wrong directionality for Vec(Flipped()) Create Chisel IR Port() in a way that Converter is happy with. Also add more extensive test suite for future-proofing. Close #1063 * Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3 and deal with the subsequent fallout. Move Aggregate, Clock, Mem, Printf, Reg Move almost all chisel3.core definitions to chisel3 or chisel3.experimental Revive core package object to provide aliases for moved definitions. Cleanup package definitions; eliminate ambiguous implicits Move more definitions to experimental. Extract BaseModule, DataMirror, ExtModule, IO into their own files. Put BitPat back in chisel3.util More experimental motion - avoid multiple import definitions. Add experimental.FixedPoint alias Add EnumType definition to core package. Update deprecated messages to refer to correct object Move FixedPoint into the experimental package (but keep it in Bits.scala). Add missing implicits to core/package - compatibility Cleanup: update ScalaDoc references; remove unused imports Add Reset alias to core/package Use common 3.2 version in deprecation warning Move Binding from core to internal. Optimize imports. Repair IntelliJ's overly cleanliness. Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3 and deal with the subsequent fallout. Move Aggregate, Clock, Mem, Printf, Reg Move almost all chisel3.core definitions to chisel3 or chisel3.experimental Revive core package object to provide aliases for moved definitions. Cleanup package definitions; eliminate ambiguous implicits Move more definitions to experimental. Extract BaseModule, DataMirror, ExtModule, IO into their own files. Add EnumType definition to core package. Update deprecated messages to refer to correct object Move FixedPoint into the experimental package (but keep it in Bits.scala). Add missing implicits to core/package - compatibility Cleanup: update ScalaDoc references; remove unused imports Use common 3.2 version in deprecation warning Move Binding from core to internal. Optimize imports. Merge cleanup. Remove unused import Bump core deprecation to 3.3 Move DontCare back into Data.scala inside package internal Re-indent experimental/internal package code Move code back to original files - facilitate comparison with other branches Some code motion, update imports, minimize master differences Move exceptions up to chisel3 package object - they're part of the interface. More master diff minimization. Fix minor discrepancies with repackagecore-testbed * Remove redundant imports As part of its import updating process, IntelliJ converted some import statements to `import package.{object, _}`. Is this intended to show an explicit dependency on `package.object` and a further dependency on `package` implicits? Unsure. Replace these with `import package._` * Move the BaseModule object into the internal package.
2019-05-13RawModule with no reset should be able to use withClock method. (#1065)Chick Markley
* RawModule with no reset should be able to use withClock method. - refactor ClockAndReset - now has `clockOpt: Option[Clock]` and `resetOpt: Option[Reset]` constructor params - convenience methods clock and reset tries to deref the option - ClockAndReset.empty is factory method for (None, None) - In Builder - forcedClock does not check resetOpt now - forcedReset does not check clockOpt now - withClock no longer looks at resetOpt - withReset no longer looks at clockOpt - Module starts with empty ClockAndReset * RawModule with no reset should be able to use withClock method. Refactor again based on @ducky64 comments - refactor away ClockAndReset, now builder just has a - currentClock - currentReset - withClock, withRest, withClockAndReset just use these fields directly * RawModule with no reset should be able to use withClock method. - Fixed typo in withReset handler, now picks up new reset
2019-05-13Merge pull request #1022 from freechipsproject/cleanup-scaladocSchuyler Eldridge
Miscellaneous Scaladoc Cleanup
2019-05-13Fix miscellaneous Scaladoc warningsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-12Cleanup loadMemoryFromFile documentationSchuyler Eldridge
This moves the documentation for loadMemoryFromFile onto the object as opposed to the apply method. This includes additional cleanup in terms of fixing uses of "$", topical grammar/capitalization, and adding more outbound links. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-12Remove deprecated @usecaseSchuyler Eldridge
This removes uses of @usecase. This is deprecated in Scala 2.13.x. Additionally, scala generious spurious warnings if you use @usecase in a non-abstract class. (It thinks that this is an abstract member of something concrete.) The guidance from upstream Scala is to be explicit about how to use your API via @example. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-12Add sources to ScaladocSchuyler Eldridge
This uses the `-sourcepath` and `-doc-source-url` options when generating Scaladoc in add a link to the Chisel3 GitHub source file. This is setup to link to master if a "-SNAPSHOT" version is used. If the documentation is built for a non-snapshot version, then this will use the "v$version" branch on GitHub. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-10Merge pull request #1094 from freechipsproject/lfsr16-deprecate-3.2Schuyler Eldridge
Change LFSR16 deprecation from 3.3 -> 3.2
2019-05-10Change LFSR16 deprecation from 3.3 -> 3.2Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-10Augment LFSR16 test to test the enable as wellAndrew Waterman
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-02 20:34:45 +0000