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authorSchuyler Eldridge2019-05-03 13:00:05 -0400
committerSchuyler Eldridge2019-05-22 16:17:17 -0400
commit0ac473b5f80b9627a06fc5caa052899680fd13cb (patch)
tree79e6ec909076ecbd58372da3c247e985f34e8023
parent121e3d87598f2056b76846472970620d046c2487 (diff)
Add chisel3.stage.phases.MaybeFirrtlStage
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
-rw-r--r--src/main/scala/chisel3/stage/phases/MaybeFirrtlStage.scala19
1 files changed, 19 insertions, 0 deletions
diff --git a/src/main/scala/chisel3/stage/phases/MaybeFirrtlStage.scala b/src/main/scala/chisel3/stage/phases/MaybeFirrtlStage.scala
new file mode 100644
index 00000000..f830c182
--- /dev/null
+++ b/src/main/scala/chisel3/stage/phases/MaybeFirrtlStage.scala
@@ -0,0 +1,19 @@
+// See LICENSE for license details.
+
+package chisel3.stage.phases
+
+import chisel3.stage.NoRunFirrtlCompilerAnnotation
+
+import firrtl.AnnotationSeq
+import firrtl.options.Phase
+import firrtl.stage.FirrtlStage
+
+/** Run [[firrtl.stage.FirrtlStage]] if a [[chisel3.stage.NoRunFirrtlCompilerAnnotation]] is not present.
+ */
+class MaybeFirrtlStage extends Phase {
+
+ def transform(annotations: AnnotationSeq): AnnotationSeq = annotations
+ .collectFirst { case NoRunFirrtlCompilerAnnotation => annotations }
+ .getOrElse { (new FirrtlStage).transform(annotations) }
+
+}