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AgeCommit message (Expand)Author
2019-12-11- add simple test of IntervalRange helperschick
2019-12-11- Change getPossibleValues of Interval to return a NumericRange former Seq ma...chick
2019-12-06Revert "Compat compile options macro (#1253)" (#1268)Jack Koenig
2019-12-04Add ChiselEnum to BundleLiterals (#1215)Zhuanhao Wu
2019-12-02Remove Jenkins CI from .mergify.yml (#1264)Jack Koenig
2019-12-02Fix asTypeOf for Clock (#1258)Jack Koenig
2019-11-29Merge pull request #1260 from freechipsproject/ccc20-extensionSchuyler Eldridge
2019-11-29Update README to reflect CCC20 ExtensionSchuyler Eldridge
2019-11-29Fix deprecation warning that leaks into user code (#1256)Jack Koenig
2019-11-29Compat compile options macro (#1253)Jack Koenig
2019-11-27Fix bidirectional Wire with Analog (#1252)Jack Koenig
2019-11-22Add binary comp. check to mergify bpAdam Izraelevitz
2019-11-22Fix mergify to backports: omit jenkins CI (#1246)Adam Izraelevitz
2019-11-22Create .mergify.yml (#1244)Adam Izraelevitz
2019-11-21Add CCC20 Info at README top (#1243)Schuyler Eldridge
2019-11-17Improve error message when assigning from Seq to Vec (#1239)Andrew Waterman
2019-11-15Enable @chiselName on non-module classes (#1209)John's Brew
2019-11-12Add brief description of (current) chisel versioning and version recommendati...Jim Lawson
2019-11-06Merge pull request #1201 from freechipsproject/full-MuxLookupSchuyler Eldridge
2019-11-05Add tests for exhaustive MuxLookup optimizationAlbert Magyar
2019-11-05Don't use MuxLookup default for full mappingSchuyler Eldridge
2019-11-05Support literals cast to aggregates as async reset reg init values (#1225)Jack Koenig
2019-11-05Bump master SNAPSHOT version. (#1227)Jim Lawson
2019-11-02Merge pull request #1224 from freechipsproject/issue-1223Schuyler Eldridge
2019-11-02Tests for anonymous/class-in-module desiredNameSchuyler Eldridge
2019-11-02Better anonymous and class-in-function desiredNameSchuyler Eldridge
2019-10-23Merge pull request #1216 from freechipsproject/non-private-ChiselStage-targetsSchuyler Eldridge
2019-10-23Make ChiselStage targets not privateColin Schmidt
2019-10-21Merge pull request #1175 from freechipsproject/bore-nameSchuyler Eldridge
2019-10-21Add BoringUtils.bore test for internal boringSchuyler Eldridge
2019-10-21Fix BoringUtils.bore for internal boringSchuyler Eldridge
2019-10-18Interval Data Type Support for Chisel (#1210)Chick Markley
2019-10-08Fix direction of dynamic index in complex Vec (#1196)Jack Koenig
2019-10-07Merge pull request #1194 from freechipsproject/issue-1166Schuyler Eldridge
2019-10-07Improve desiredName for nested objects/classesSchuyler Eldridge
2019-09-30Bump sbt to 1.3.2 (#1188)Jim Lawson
2019-09-27Merge pull request #1193 from freechipsproject/readme-fixSchuyler Eldridge
2019-09-26More README.md fixesSchuyler Eldridge
2019-09-25Merge pull request #1191 from freechipsproject/readme-fixSchuyler Eldridge
2019-09-25Use raw link for FIR filterSchuyler Eldridge
2019-09-25Merge pull request #1190 from freechipsproject/readme-fixSchuyler Eldridge
2019-09-25Simplify data types README descriptionSchuyler Eldridge
2019-09-25Use full URL links for imagesSchuyler Eldridge
2019-09-25Add graphviz type hierarchy with built svg/pngSchuyler Eldridge
2019-09-25Use line instead of empty H1 in README.mdSchuyler Eldridge
2019-09-19Add running one testcase to mill (#1103)Leway Colin
2019-09-17Updated to sbt 1.3.0 (#1181)Boris V.Kuznetsov
2019-09-16Da steve101 tree reduce (#485)Jack Koenig
2019-09-16Bump Scala to 2.12.10 (#1179)Jack Koenig
2019-09-13Add requirements to Queue class (#1176)Jack Koenig
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