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authorJack Koenig2019-09-13 12:19:12 -0700
committerGitHub2019-09-13 12:19:12 -0700
commit4af6db34e865b44cc68ed114d35ca6016a37d265 (patch)
tree4f99dadb5dbdea7ea1411dc84586236c0af0d381
parent14503966b017d160e46cc7e401c2ffa2c39212e8 (diff)
Add requirements to Queue class (#1176)
FIRRTL barfs on negative and zero-sized memories
-rw-r--r--src/main/scala/chisel3/util/Decoupled.scala8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 841f90e6..c20c1eb3 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -191,7 +191,8 @@ class Queue[T <: Data](gen: T,
flow: Boolean = false)
(implicit compileOptions: chisel3.CompileOptions)
extends Module() {
-
+ require(entries > -1, "Queue must have non-negative number of entries")
+ require(entries != 0, "Use companion object Queue.apply for zero entries")
val genType = if (compileOptions.declaredTypeMustBeUnbound) {
requireIsChiselType(gen)
gen
@@ -283,7 +284,6 @@ object Queue
enq.ready := deq.ready
deq
} else {
- require(entries > 0)
val q = Module(new Queue(chiselTypeOf(enq.bits), entries, pipe, flow))
q.io.enq.valid := enq.valid // not using <> so that override is allowed
q.io.enq.bits := enq.bits
@@ -302,9 +302,9 @@ object Queue
enq: ReadyValidIO[T],
entries: Int = 2,
pipe: Boolean = false,
- flow: Boolean = false): IrrevocableIO[T] = {
- require(entries > 0) // Zero-entry queues don't guarantee Irrevocability
+ flow: Boolean = false): IrrevocableIO[T] = {
val deq = apply(enq, entries, pipe, flow)
+ require(entries > 0, "Zero-entry queues don't guarantee Irrevocability")
val irr = Wire(new IrrevocableIO(deq.bits))
irr.bits := deq.bits
irr.valid := deq.valid