3 files changed, 4 insertions, 8 deletions
diff --git a/src/main/scala/chisel3/util/experimental/BoringUtils.scala b/src/main/scala/chisel3/util/experimental/BoringUtils.scala
index a6f2d52a..da5b3fd0 100644
--- a/src/main/scala/chisel3/util/experimental/BoringUtils.scala
+++ b/src/main/scala/chisel3/util/experimental/BoringUtils.scala
@@ -4,13 +4,12 @@ package chisel3.util.experimental
 
 import chisel3._
 import chisel3.experimental.{ChiselAnnotation, RunFirrtlTransform, annotate}
-import chisel3.internal.{InstanceId, NamedComponent}
+import chisel3.internal.{InstanceId, NamedComponent, Namespace}
 import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation}
 import firrtl.passes.wiring.{WiringTransform, SourceAnnotation, SinkAnnotation}
 import firrtl.annotations.{ModuleName, ComponentName}
 
 import scala.concurrent.SyncVar
-import chisel3.internal.Namespace
 
 /** An exception related to BoringUtils
   * @param message the exception message
diff --git a/src/main/scala/chisel3/util/experimental/Inline.scala b/src/main/scala/chisel3/util/experimental/Inline.scala
index 753c36af..7e8a35fb 100644
--- a/src/main/scala/chisel3/util/experimental/Inline.scala
+++ b/src/main/scala/chisel3/util/experimental/Inline.scala
@@ -3,12 +3,11 @@
 package chisel3.util.experimental
 
 import chisel3._
-import chisel3.internal.InstanceId
 import chisel3.experimental.{BaseModule, ChiselAnnotation, RunFirrtlTransform}
 import firrtl.Transform
 import firrtl.passes.{InlineAnnotation, InlineInstances}
 import firrtl.transforms.{NoDedupAnnotation, FlattenAnnotation, Flatten}
-import firrtl.annotations.{CircuitName, ModuleName, ComponentName, Annotation}
+import firrtl.annotations.Annotation
 
 /** Inlines an instance of a module
   *
diff --git a/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala b/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
index 2d23de38..3d14b5c2 100644
--- a/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
+++ b/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
@@ -3,10 +3,8 @@
 package chisel3.util.experimental
 
 import chisel3._
-import chisel3.experimental.annotate
-// import chisel3.InstanceId
-import chisel3.experimental.{ChiselAnnotation, RunFirrtlTransform}
-import firrtl.annotations.{MemoryLoadFileType, _}
+import chisel3.experimental.{RunFirrtlTransform, annotate, ChiselAnnotation}
+import firrtl.annotations._
 import firrtl.ir.{Module => _, _}
 import firrtl.transforms.BlackBoxInlineAnno
 import firrtl.Mappers._