12 files changed, 33 insertions, 21 deletions
diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala
index 6cba497e..b8a239d0 100644
--- a/src/main/scala/chisel3/util/BitPat.scala
+++ b/src/main/scala/chisel3/util/BitPat.scala
@@ -4,10 +4,10 @@ package chisel3.util
 
 import scala.language.experimental.macros
 import chisel3._
-import chisel3.core.CompileOptions
 import chisel3.internal.chiselRuntimeDeprecated
 import chisel3.internal.sourceinfo.{SourceInfo, SourceInfoTransform}
 
+
 object BitPat {
   /** Parses a bit pattern string into (bits, mask, width).
     *
@@ -77,6 +77,28 @@ object BitPat {
     val len = if (x.isWidthKnown) x.getWidth else 0
     apply("b" + x.litValue.toString(2).reverse.padTo(len, "0").reverse.mkString)
   }
+
+  implicit class fromUIntToBitPatComparable(x: UInt) extends SourceInfoDoc {
+    import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
+
+    import scala.language.experimental.macros
+
+    final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg
+    final def =/= (that: BitPat): Bool = macro SourceInfoTransform.thatArg
+
+    /** @group SourceInfoTransformMacro */
+    def do_=== (that: BitPat)  // scalastyle:ignore method.name
+               (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = that === x
+    /** @group SourceInfoTransformMacro */
+    def do_=/= (that: BitPat)  // scalastyle:ignore method.name
+               (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = that =/= x
+
+    final def != (that: BitPat): Bool = macro SourceInfoTransform.thatArg
+    @chiselRuntimeDeprecated
+    @deprecated("Use '=/=', which avoids potential precedence problems", "chisel3")
+    def do_!= (that: BitPat)  // scalastyle:ignore method.name
+              (implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = that != x
+  }
 }
 
 /** Bit patterns are literals with masks, used to represent values with don't
diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala
index 1692e083..bbed5f07 100644
--- a/src/main/scala/chisel3/util/Bitwise.scala
+++ b/src/main/scala/chisel3/util/Bitwise.scala
@@ -6,7 +6,6 @@
 package chisel3.util
 
 import chisel3._
-import chisel3.core.SeqUtils
 
 /** Creates repetitions of each bit of the input in order.
   *
diff --git a/src/main/scala/chisel3/util/Cat.scala b/src/main/scala/chisel3/util/Cat.scala
index 78801541..ee01c6e6 100644
--- a/src/main/scala/chisel3/util/Cat.scala
+++ b/src/main/scala/chisel3/util/Cat.scala
@@ -3,7 +3,6 @@
 package chisel3.util
 
 import chisel3._
-import chisel3.core.SeqUtils
 
 /** Concatenates elements of the input, in order, together.
   *
diff --git a/src/main/scala/chisel3/util/Conditional.scala b/src/main/scala/chisel3/util/Conditional.scala
index 3630f8ad..c87c2cb6 100644
--- a/src/main/scala/chisel3/util/Conditional.scala
+++ b/src/main/scala/chisel3/util/Conditional.scala
@@ -7,7 +7,6 @@ package chisel3.util
 
 import scala.language.reflectiveCalls
 import scala.language.experimental.macros
-import scala.reflect.runtime.universe._
 import scala.reflect.macros.blackbox._
 
 import chisel3._
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 7ab13922..047973f5 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -6,7 +6,7 @@
 package chisel3.util
 
 import chisel3._
-import chisel3.experimental.{DataMirror, Direction, requireIsChiselType}
+import chisel3.experimental.{DataMirror, Direction, MultiIOModule, requireIsChiselType}
 import chisel3.internal.naming._  // can't use chisel3_ version because of compile order
 
 /** An I/O Bundle containing 'valid' and 'ready' signals that handshake
@@ -21,7 +21,7 @@ abstract class ReadyValidIO[+T <: Data](gen: T) extends Bundle
 {
   // Compatibility hack for rocket-chip
   private val genType = (DataMirror.internal.isSynthesizable(gen), chisel3.internal.Builder.currentModule) match {
-    case (true, Some(module: chisel3.core.MultiIOModule))
+    case (true, Some(module: MultiIOModule))
         if !module.compileOptions.declaredTypeMustBeUnbound => chiselTypeOf(gen)
     case _ => gen
   }
@@ -186,7 +186,7 @@ class Queue[T <: Data](gen: T,
                        val entries: Int,
                        pipe: Boolean = false,
                        flow: Boolean = false)
-                      (implicit compileOptions: chisel3.core.CompileOptions)
+                      (implicit compileOptions: chisel3.CompileOptions)
     extends Module() {
   @deprecated("Module constructor with override _reset deprecated, use withReset", "chisel3")
   def this(gen: T, entries: Int, pipe: Boolean, flow: Boolean, override_reset: Option[Bool]) = {
diff --git a/src/main/scala/chisel3/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala
index 24ea0470..4c89acdd 100644
--- a/src/main/scala/chisel3/util/ImplicitConversions.scala
+++ b/src/main/scala/chisel3/util/ImplicitConversions.scala
@@ -12,6 +12,6 @@ import scala.language.implicitConversions
 object ImplicitConversions {
   // The explicit fromIntToLiteral resolves an ambiguous conversion between fromIntToLiteral and
   // UInt.asUInt.
-  implicit def intToUInt(x: Int): UInt = chisel3.core.fromIntToLiteral(x).asUInt
+  implicit def intToUInt(x: Int): UInt = chisel3.fromIntToLiteral(x).asUInt
   implicit def booleanToBool(x: Boolean): Bool = x.B
 }
diff --git a/src/main/scala/chisel3/util/MixedVec.scala b/src/main/scala/chisel3/util/MixedVec.scala
index 9b70cd41..70b0656f 100644
--- a/src/main/scala/chisel3/util/MixedVec.scala
+++ b/src/main/scala/chisel3/util/MixedVec.scala
@@ -3,7 +3,7 @@
 package chisel3.util
 
 import chisel3._
-import chisel3.core.{Data, requireIsChiselType, requireIsHardware}
+import chisel3.internal.requireIsChiselType
 
 import scala.collection.immutable.ListMap
 
@@ -11,7 +11,7 @@ import scala.collection.immutable.ListMap
   * Create a MixedVec wire with default values as specified, and type of each element inferred from
   * those default values.
   *
-  * This is analogous to [[chisel3.core.VecInit]].
+  * This is analogous to [[VecInit]].
   * @return MixedVec with given values assigned
   *
   * @example {{{
diff --git a/src/main/scala/chisel3/util/Mux.scala b/src/main/scala/chisel3/util/Mux.scala
index 1fa7518e..342531bd 100644
--- a/src/main/scala/chisel3/util/Mux.scala
+++ b/src/main/scala/chisel3/util/Mux.scala
@@ -6,7 +6,6 @@
 package chisel3.util
 
 import chisel3._
-import chisel3.core.SeqUtils
 
 /** Builds a Mux tree out of the input signal vector using a one hot encoded
   * select signal. Returns the output of the Mux tree.
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index c6458b9d..ef27263e 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -6,8 +6,6 @@
 package chisel3.util
 
 import chisel3._
-import chisel3.core.CompileOptions
-import chisel3.experimental.DataMirror
 
 /** A [[Bundle]] that adds a `valid` bit to some data. This indicates that the user expects a "valid" interface between
   * a producer and a consumer. Here, the producer asserts the `valid` bit when data on the `bits` line contains valid
diff --git a/src/main/scala/chisel3/util/experimental/BoringUtils.scala b/src/main/scala/chisel3/util/experimental/BoringUtils.scala
index a6f2d52a..da5b3fd0 100644
--- a/src/main/scala/chisel3/util/experimental/BoringUtils.scala
+++ b/src/main/scala/chisel3/util/experimental/BoringUtils.scala
@@ -4,13 +4,12 @@ package chisel3.util.experimental
 
 import chisel3._
 import chisel3.experimental.{ChiselAnnotation, RunFirrtlTransform, annotate}
-import chisel3.internal.{InstanceId, NamedComponent}
+import chisel3.internal.{InstanceId, NamedComponent, Namespace}
 import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation}
 import firrtl.passes.wiring.{WiringTransform, SourceAnnotation, SinkAnnotation}
 import firrtl.annotations.{ModuleName, ComponentName}
 
 import scala.concurrent.SyncVar
-import chisel3.internal.Namespace
 
 /** An exception related to BoringUtils
   * @param message the exception message
diff --git a/src/main/scala/chisel3/util/experimental/Inline.scala b/src/main/scala/chisel3/util/experimental/Inline.scala
index 753c36af..7e8a35fb 100644
--- a/src/main/scala/chisel3/util/experimental/Inline.scala
+++ b/src/main/scala/chisel3/util/experimental/Inline.scala
@@ -3,12 +3,11 @@
 package chisel3.util.experimental
 
 import chisel3._
-import chisel3.internal.InstanceId
 import chisel3.experimental.{BaseModule, ChiselAnnotation, RunFirrtlTransform}
 import firrtl.Transform
 import firrtl.passes.{InlineAnnotation, InlineInstances}
 import firrtl.transforms.{NoDedupAnnotation, FlattenAnnotation, Flatten}
-import firrtl.annotations.{CircuitName, ModuleName, ComponentName, Annotation}
+import firrtl.annotations.Annotation
 
 /** Inlines an instance of a module
   *
diff --git a/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala b/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
index 2d23de38..3d14b5c2 100644
--- a/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
+++ b/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala
@@ -3,10 +3,8 @@
 package chisel3.util.experimental
 
 import chisel3._
-import chisel3.experimental.annotate
-// import chisel3.InstanceId
-import chisel3.experimental.{ChiselAnnotation, RunFirrtlTransform}
-import firrtl.annotations.{MemoryLoadFileType, _}
+import chisel3.experimental.{RunFirrtlTransform, annotate, ChiselAnnotation}
+import firrtl.annotations._
 import firrtl.ir.{Module => _, _}
 import firrtl.transforms.BlackBoxInlineAnno
 import firrtl.Mappers._