2 files changed, 5 insertions, 7 deletions
diff --git a/src/main/scala/chisel3/internal/firrtl/Converter.scala b/src/main/scala/chisel3/internal/firrtl/Converter.scala
index 9366bea2..cdc55b59 100644
--- a/src/main/scala/chisel3/internal/firrtl/Converter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Converter.scala
@@ -2,14 +2,13 @@
 
 package chisel3.internal.firrtl
 import chisel3._
-import chisel3.core.{SpecifiedDirection, EnumType}
 import chisel3.experimental._
 import chisel3.internal.sourceinfo.{NoSourceInfo, SourceLine, SourceInfo}
 import firrtl.{ir => fir}
 import chisel3.internal.{castToInt, throwException}
 
 import scala.annotation.tailrec
-import scala.collection.immutable.{Queue}
+import scala.collection.immutable.Queue
 
 private[chisel3] object Converter {
   // TODO modeled on unpack method on Printable, refactor?
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 050c8b72..2f1b75b0 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -2,9 +2,8 @@
 
 package chisel3.internal.firrtl
 import chisel3._
-import chisel3.core.{SpecifiedDirection, EnumType}
 import chisel3.experimental._
-import chisel3.internal.sourceinfo.{NoSourceInfo, SourceLine}
+import chisel3.internal.BaseBlackBox
 
 private[chisel3] object Emitter {
   def emit(circuit: Circuit): String = new Emitter(circuit).toString
@@ -28,7 +27,7 @@ private class Emitter(circuit: Circuit) {
 
   private def emitType(d: Data, clearDir: Boolean = false): String = d match { // scalastyle:ignore cyclomatic.complexity line.size.limit
     case d: Clock => "Clock"
-    case d: chisel3.core.EnumType => s"UInt${d.width}"
+    case d: EnumType => s"UInt${d.width}"
     case d: UInt => s"UInt${d.width}"
     case d: SInt => s"SInt${d.width}"
     case d: FixedPoint => s"Fixed${d.width}${d.binaryPoint}"
@@ -110,8 +109,8 @@ private class Emitter(circuit: Circuit) {
   /** Generates the FIRRTL module declaration.
     */
   private def moduleDecl(m: Component): String = m.id match {
-    case _: chisel3.core.BaseBlackBox => newline + s"extmodule ${m.name} : "
-    case _: chisel3.core.RawModule => newline + s"module ${m.name} : "
+    case _: BaseBlackBox => newline + s"extmodule ${m.name} : "
+    case _: RawModule => newline + s"module ${m.name} : "
   }
 
   /** Generates the FIRRTL module definition.