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Diffstat (limited to 'src/main/scala/Chisel/CoreUtil.scala')
| -rw-r--r-- | src/main/scala/Chisel/CoreUtil.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/Chisel/CoreUtil.scala b/src/main/scala/Chisel/CoreUtil.scala index bad7799a..708b516e 100644 --- a/src/main/scala/Chisel/CoreUtil.scala +++ b/src/main/scala/Chisel/CoreUtil.scala @@ -9,7 +9,7 @@ import internal.firrtl._ import scala.language.experimental.macros import scala.reflect.macros.blackbox.Context -object assert { +object assert { // scalastyle:ignore object.name /** Checks for a condition to be valid in the circuit at all times. If the * condition evaluates to false, the circuit simulation stops with an error. * @@ -70,7 +70,7 @@ object assert { } } -object printf { +object printf { // scalastyle:ignore object.name /** Prints a message in simulation. * * Does not fire when in reset (defined as the encapsulating Module's |