8 files changed, 23 insertions, 15 deletions
diff --git a/src/main/scala/Chisel/Aggregate.scala b/src/main/scala/Chisel/Aggregate.scala
index 6bf656a9..de685d0a 100644
--- a/src/main/scala/Chisel/Aggregate.scala
+++ b/src/main/scala/Chisel/Aggregate.scala
@@ -306,7 +306,7 @@ class Bundle extends Aggregate(NO_DIR) {
   private[Chisel] lazy val flatten = namedElts.flatMap(_._2.flatten)
   private[Chisel] def addElt(name: String, elt: Data): Unit =
     namedElts += name -> elt
-  private[Chisel] override def _onModuleClose: Unit =
+  private[Chisel] override def _onModuleClose: Unit = // scalastyle:ignore method.name
     for ((name, elt) <- namedElts) { elt.setRef(this, _namespace.name(name)) }
 
   override def cloneType : this.type = {
diff --git a/src/main/scala/Chisel/CoreUtil.scala b/src/main/scala/Chisel/CoreUtil.scala
index bad7799a..708b516e 100644
--- a/src/main/scala/Chisel/CoreUtil.scala
+++ b/src/main/scala/Chisel/CoreUtil.scala
@@ -9,7 +9,7 @@ import internal.firrtl._
 import scala.language.experimental.macros
 import scala.reflect.macros.blackbox.Context
 
-object assert {
+object assert { // scalastyle:ignore object.name
   /** Checks for a condition to be valid in the circuit at all times. If the
     * condition evaluates to false, the circuit simulation stops with an error.
     *
@@ -70,7 +70,7 @@ object assert {
   }
 }
 
-object printf {
+object printf { // scalastyle:ignore object.name
   /** Prints a message in simulation.
     *
     * Does not fire when in reset (defined as the encapsulating Module's
diff --git a/src/main/scala/Chisel/Data.scala b/src/main/scala/Chisel/Data.scala
index ac3bd9ab..3fa3dc20 100644
--- a/src/main/scala/Chisel/Data.scala
+++ b/src/main/scala/Chisel/Data.scala
@@ -94,8 +94,11 @@ abstract class Data(dirArg: Direction) extends HasId {
     var i = 0
     val wire = Wire(this.cloneType)
     val bits =
-      if (n.width.known && n.width.get >= wire.width.get) n
-      else Wire(n.cloneTypeWidth(wire.width), init = n)
+      if (n.width.known && n.width.get >= wire.width.get) {
+        n
+      } else {
+        Wire(n.cloneTypeWidth(wire.width), init = n)
+      }
     for (x <- wire.flatten) {
       x := bits(i + x.getWidth-1, i)
       i += x.getWidth
@@ -124,8 +127,9 @@ object Wire {
     val x = Reg.makeType(t, null.asInstanceOf[T], init)
     pushCommand(DefWire(x))
     pushCommand(DefInvalid(x.ref))
-    if (init != null)
+    if (init != null) {
       x := init
+    }
     x
   }
 }
diff --git a/src/main/scala/Chisel/Driver.scala b/src/main/scala/Chisel/Driver.scala
index c832426e..422a4110 100644
--- a/src/main/scala/Chisel/Driver.scala
+++ b/src/main/scala/Chisel/Driver.scala
@@ -76,7 +76,7 @@ trait BackendCompilationUtilities {
         s"""-Wno-undefined-bool-conversion -O2 -DTOP_TYPE=V$dutFile -include V$dutFile.h""",
         "-Mdir", dir.toString,
         "--exe", cppHarness.toString)
-    System.out.println(s"${command.mkString(" ")}")
+    System.out.println(s"${command.mkString(" ")}") // scalastyle:ignore regex
     command
   }
 
@@ -91,7 +91,7 @@ trait BackendCompilationUtilities {
     val e = Process(s"./V${prefix}", dir) !
       ProcessLogger(line => {
         triggered = triggered || line.contains(assertionMsg)
-        System.out.println(line)
+        System.out.println(line) // scalastyle:ignore regex
       })
     triggered
   }
diff --git a/src/main/scala/Chisel/internal/Builder.scala b/src/main/scala/Chisel/internal/Builder.scala
index 73dd5906..f9d27a61 100644
--- a/src/main/scala/Chisel/internal/Builder.scala
+++ b/src/main/scala/Chisel/internal/Builder.scala
@@ -41,13 +41,13 @@ private[Chisel] class IdGen {
 }
 
 private[Chisel] trait HasId {
-  private[Chisel] def _onModuleClose {}
+  private[Chisel] def _onModuleClose {} // scalastyle:ignore method.name
   private[Chisel] val _parent = Builder.dynamicContext.currentModule
   _parent.foreach(_.addId(this))
 
   private[Chisel] val _id = Builder.idGen.next
-  override def hashCode = _id.toInt
-  override def equals(that: Any) = that match {
+  override def hashCode: Int = _id.toInt
+  override def equals(that: Any): Boolean = that match {
     case x: HasId => _id == x._id
     case _ => false
   }
diff --git a/src/main/scala/Chisel/internal/firrtl/IR.scala b/src/main/scala/Chisel/internal/firrtl/IR.scala
index 4c039e9a..1e06a663 100644
--- a/src/main/scala/Chisel/internal/firrtl/IR.scala
+++ b/src/main/scala/Chisel/internal/firrtl/IR.scala
@@ -169,9 +169,11 @@ case class Printf(clk: Arg, formatIn: String, ids: Seq[Arg]) extends Command {
   def format: String = {
     def escaped(x: Char) = {
       require(x.toInt >= 0)
-      if (x == '"' || x == '\\') s"\\${x}"
-      else if (x == '\n') "\\n"
-      else {
+      if (x == '"' || x == '\\') {
+        s"\\${x}"
+      } else if (x == '\n') {
+        "\\n"
+      } else {
         require(x.toInt >= 32) // TODO \xNN once FIRRTL issue #59 is resolved
         x
       }
diff --git a/src/main/scala/Chisel/throwException.scala b/src/main/scala/Chisel/throwException.scala
index 1932bec8..702884aa 100644
--- a/src/main/scala/Chisel/throwException.scala
+++ b/src/main/scala/Chisel/throwException.scala
@@ -3,6 +3,7 @@
 package Chisel
 
 @deprecated("throwException doesn't exist in Chisel3", "3.0.0")
+@throws(classOf[Exception])
 object throwException {
   def apply(s: String, t: Throwable = null) = {
     val xcpt = new Exception(s, t)
diff --git a/src/main/scala/Chisel/util/Counter.scala b/src/main/scala/Chisel/util/Counter.scala
index 3a9db309..872e830a 100644
--- a/src/main/scala/Chisel/util/Counter.scala
+++ b/src/main/scala/Chisel/util/Counter.scala
@@ -17,8 +17,9 @@ class Counter(val n: Int) {
     if (n > 1) {
       val wrap = value === UInt(n-1)
       value := value + UInt(1)
-      if (!isPow2(n))
+      if (!isPow2(n)) {
         when (wrap) { value := UInt(0) }
+      }
       wrap
     } else {
       Bool(true)