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authorJim Lawson2016-04-26 11:06:16 -0700
committerJim Lawson2016-04-26 11:06:16 -0700
commit09958f63470697188e1ed1a01c7ea39b8c56e7ef (patch)
tree9c0d8ef8d69cbe74b5e56e8474f0304aacdadc6b /src/main/scala/Chisel/CoreUtil.scala
parent19046381ae319915c4e8fff7b108e6b5dd100509 (diff)
Scalastyle fixes and "ignores". - No functional changes.
Diffstat (limited to 'src/main/scala/Chisel/CoreUtil.scala')
-rw-r--r--src/main/scala/Chisel/CoreUtil.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/Chisel/CoreUtil.scala b/src/main/scala/Chisel/CoreUtil.scala
index bad7799a..708b516e 100644
--- a/src/main/scala/Chisel/CoreUtil.scala
+++ b/src/main/scala/Chisel/CoreUtil.scala
@@ -9,7 +9,7 @@ import internal.firrtl._
import scala.language.experimental.macros
import scala.reflect.macros.blackbox.Context
-object assert {
+object assert { // scalastyle:ignore object.name
/** Checks for a condition to be valid in the circuit at all times. If the
* condition evaluates to false, the circuit simulation stops with an error.
*
@@ -70,7 +70,7 @@ object assert {
}
}
-object printf {
+object printf { // scalastyle:ignore object.name
/** Prints a message in simulation.
*
* Does not fire when in reset (defined as the encapsulating Module's