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-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Module.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index dfb9081c..0e919d3c 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -70,7 +70,7 @@ object Module {
/** Returns the implicit Clock */
def clock: Clock = Builder.forcedClock
/** Returns the implicit Reset */
- def reset: Bool = Builder.forcedReset
+ def reset: Reset = Builder.forcedReset
}
/** Abstract base class for Modules, an instantiable organizational unit for RTL.