diff options
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Module.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala index 88013bae..89dd2dee 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala @@ -180,7 +180,7 @@ abstract class BaseModule extends HasId { def desiredName = this.getClass.getName.split('.').last /** Legalized name of this module. */ - final val name = Builder.globalNamespace.name(desiredName) + final lazy val name = Builder.globalNamespace.name(desiredName) /** Returns a FIRRTL ModuleName that references this object * @note Should not be called until circuit elaboration is complete |