diff options
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Module.scala | 2 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/Module.scala | 9 |
2 files changed, 10 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala index 88013bae..89dd2dee 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala @@ -180,7 +180,7 @@ abstract class BaseModule extends HasId { def desiredName = this.getClass.getName.split('.').last /** Legalized name of this module. */ - final val name = Builder.globalNamespace.name(desiredName) + final lazy val name = Builder.globalNamespace.name(desiredName) /** Returns a FIRRTL ModuleName that references this object * @note Should not be called until circuit elaboration is complete diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index 968e7578..dc44838a 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -62,6 +62,12 @@ class ModuleRewrap extends Module { val inst2 = Module(inst) } +class ModuleWrapper(gen: => Module) extends Module { + val io = IO(new Bundle{}) + val child = Module(gen) + override lazy val desiredName = s"${child.desiredName}Wrapper" +} + class ModuleSpec extends ChiselPropSpec { property("ModuleVec should elaborate") { @@ -138,4 +144,7 @@ class ModuleSpec extends ChiselPropSpec { "a" -> m.a, "b" -> m.b)) }) } + property("A desiredName parameterized by a submodule should work") { + Driver.elaborate(() => new ModuleWrapper(new ModuleWire)).name should be ("ModuleWireWrapper") + } } |