diff options
Diffstat (limited to 'chiselFrontend/src/main/scala/Chisel/Aggregate.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/Chisel/Aggregate.scala | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala b/chiselFrontend/src/main/scala/Chisel/Aggregate.scala index 8af4e9e9..f573592d 100644 --- a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala +++ b/chiselFrontend/src/main/scala/Chisel/Aggregate.scala @@ -167,9 +167,6 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int) private[Chisel] lazy val flatten: IndexedSeq[Bits] = (0 until length).flatMap(i => this.apply(i).flatten) - /** Reinterpret cast to UInt. */ - def asUInt(): UInt = macro SourceInfoTransform.noArg - def do_asUInt(implicit sourceInfo: SourceInfo): UInt = SeqUtils.do_asUInt(this.flatten).asUInt() for ((elt, i) <- self zipWithIndex) @@ -347,9 +344,6 @@ class Bundle extends Aggregate(NO_DIR) { private[Chisel] def addElt(name: String, elt: Data): Unit = namedElts += name -> elt - /** Reinterpret cast to UInt. */ - def asUInt(): UInt = macro SourceInfoTransform.noArg - def do_asUInt(implicit sourceInfo: SourceInfo): UInt = SeqUtils.do_asUInt(this.flatten).asUInt() private[Chisel] override def _onModuleClose: Unit = // scalastyle:ignore method.name |