diff options
| author | chick | 2016-06-06 15:32:33 -0700 |
|---|---|---|
| committer | chick | 2016-06-06 15:32:33 -0700 |
| commit | 43124af2f3eab9a3491dd2c83c1922b1b7e07c2a (patch) | |
| tree | 2f49304edeb9de95eaaec47599b812c042195ecb /chiselFrontend/src/main/scala/Chisel/Aggregate.scala | |
| parent | e98f9656591925464c42db70641d3cfa501f108a (diff) | |
moved macro def for toUInt() int to Data and made do_asUInt (the macro target) there as an abstract method.
This left clock without a do_asUInt, that has been implemented as an exception at this time
Diffstat (limited to 'chiselFrontend/src/main/scala/Chisel/Aggregate.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/Chisel/Aggregate.scala | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala b/chiselFrontend/src/main/scala/Chisel/Aggregate.scala index 8af4e9e9..f573592d 100644 --- a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala +++ b/chiselFrontend/src/main/scala/Chisel/Aggregate.scala @@ -167,9 +167,6 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int) private[Chisel] lazy val flatten: IndexedSeq[Bits] = (0 until length).flatMap(i => this.apply(i).flatten) - /** Reinterpret cast to UInt. */ - def asUInt(): UInt = macro SourceInfoTransform.noArg - def do_asUInt(implicit sourceInfo: SourceInfo): UInt = SeqUtils.do_asUInt(this.flatten).asUInt() for ((elt, i) <- self zipWithIndex) @@ -347,9 +344,6 @@ class Bundle extends Aggregate(NO_DIR) { private[Chisel] def addElt(name: String, elt: Data): Unit = namedElts += name -> elt - /** Reinterpret cast to UInt. */ - def asUInt(): UInt = macro SourceInfoTransform.noArg - def do_asUInt(implicit sourceInfo: SourceInfo): UInt = SeqUtils.do_asUInt(this.flatten).asUInt() private[Chisel] override def _onModuleClose: Unit = // scalastyle:ignore method.name |
