3 files changed, 14 insertions, 19 deletions
diff --git a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala b/chiselFrontend/src/main/scala/Chisel/Aggregate.scala
index 8af4e9e9..f573592d 100644
--- a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/Chisel/Aggregate.scala
@@ -167,9 +167,6 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int)
   private[Chisel] lazy val flatten: IndexedSeq[Bits] =
     (0 until length).flatMap(i => this.apply(i).flatten)
 
-  /** Reinterpret cast to UInt. */
-  def asUInt(): UInt = macro SourceInfoTransform.noArg
-
   def do_asUInt(implicit sourceInfo: SourceInfo): UInt = SeqUtils.do_asUInt(this.flatten).asUInt()
 
   for ((elt, i) <- self zipWithIndex)
@@ -347,9 +344,6 @@ class Bundle extends Aggregate(NO_DIR) {
   private[Chisel] def addElt(name: String, elt: Data): Unit =
     namedElts += name -> elt
 
-  /** Reinterpret cast to UInt. */
-  def asUInt(): UInt = macro SourceInfoTransform.noArg
-
   def do_asUInt(implicit sourceInfo: SourceInfo): UInt = SeqUtils.do_asUInt(this.flatten).asUInt()
 
   private[Chisel] override def _onModuleClose: Unit = // scalastyle:ignore method.name
diff --git a/chiselFrontend/src/main/scala/Chisel/Bits.scala b/chiselFrontend/src/main/scala/Chisel/Bits.scala
index bc8cc8e2..ee6b1dee 100644
--- a/chiselFrontend/src/main/scala/Chisel/Bits.scala
+++ b/chiselFrontend/src/main/scala/Chisel/Bits.scala
@@ -210,15 +210,6 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
 
   def do_asSInt(implicit sourceInfo: SourceInfo): SInt
 
-  /** Reinterpret cast to an UInt.
-    *
-    * @note value not guaranteed to be preserved: for example, a SInt of width
-    * 3 and value -1 (0b111) would become an UInt with value 7
-    */
-  final def asUInt(): UInt = macro SourceInfoTransform.noArg
-
-  def do_asUInt(implicit sourceInfo: SourceInfo): UInt
-
   /** Reinterpret cast to Bits. */
   final def asBits(): Bits = macro SourceInfoTransform.noArg
 
@@ -250,9 +241,6 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
     pushOp(DefPrim(sourceInfo, UInt(w), ConcatOp, this.ref, that.ref))
   }
 
-  @deprecated("Use asBits, which makes the reinterpret cast more explicit and actually returns Bits", "chisel3")
-  override def toBits: UInt = do_asUInt(DeprecatedSourceInfo)
-
   override def do_fromBits(that: Bits)(implicit sourceInfo: SourceInfo): this.type = {
     val res = Wire(this, null).asInstanceOf[this.type]
     res := that
diff --git a/chiselFrontend/src/main/scala/Chisel/Data.scala b/chiselFrontend/src/main/scala/Chisel/Data.scala
index adb4ff7b..b953df71 100644
--- a/chiselFrontend/src/main/scala/Chisel/Data.scala
+++ b/chiselFrontend/src/main/scala/Chisel/Data.scala
@@ -120,7 +120,15 @@ abstract class Data(dirArg: Direction) extends HasId {
   @deprecated("Best alternative, .toUInt() or if Bits really needed, .toUInt().toBits()", "chisel3")
   def toBits(): UInt = SeqUtils.do_asUInt(this.flatten)(DeprecatedSourceInfo)
 
-//  def asBits(): Bits
+  /** Reinterpret cast to a UInt.
+    *
+    * @note value not guaranteed to be preserved: for example, a SInt of width
+    * 3 and value -1 (0b111) would become an UInt with value 7
+    */
+  final def asUInt(): UInt = macro SourceInfoTransform.noArg
+
+  def do_asUInt(implicit sourceInfo: SourceInfo): UInt
+
 }
 
 object Wire {
@@ -160,4 +168,9 @@ sealed class Clock(dirArg: Direction) extends Element(dirArg, Width(1)) {
     case _: Clock => this connect that
     case _ => this badConnect that
   }
+
+  def do_asUInt(implicit sourceInfo: SourceInfo): UInt = {
+    throwException("clock cannot be interpreted as UInt")
+  }
+
 }