16 files changed, 9 insertions, 1 deletions
diff --git a/build.sbt b/build.sbt
index 3cd496bb..6fd2c48a 100644
--- a/build.sbt
+++ b/build.sbt
@@ -76,5 +76,13 @@ lazy val chiselBuildSettings = Seq (
   //  }
 )
 
+lazy val chiselFrontend = (project in file("chiselFrontend")).
+  settings(Seq(
+    scalaVersion := "2.11.7",
+    libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value
+  ))
+
 lazy val chisel = (project in file(".")).
-  settings(chiselBuildSettings: _*)
+  settings(chiselBuildSettings: _*).
+  dependsOn(chiselFrontend)
+
diff --git a/src/main/scala/Chisel/Aggregate.scala b/chiselFrontend/src/main/scala/Chisel/Aggregate.scala
index 4d35e2f0..4d35e2f0 100644
--- a/src/main/scala/Chisel/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/Chisel/Aggregate.scala
diff --git a/src/main/scala/Chisel/BitPat.scala b/chiselFrontend/src/main/scala/Chisel/BitPat.scala
index a1bf1985..a1bf1985 100644
--- a/src/main/scala/Chisel/BitPat.scala
+++ b/chiselFrontend/src/main/scala/Chisel/BitPat.scala
diff --git a/src/main/scala/Chisel/Bits.scala b/chiselFrontend/src/main/scala/Chisel/Bits.scala
index 44d9b660..44d9b660 100644
--- a/src/main/scala/Chisel/Bits.scala
+++ b/chiselFrontend/src/main/scala/Chisel/Bits.scala
diff --git a/src/main/scala/Chisel/BlackBox.scala b/chiselFrontend/src/main/scala/Chisel/BlackBox.scala
index be72934d..be72934d 100644
--- a/src/main/scala/Chisel/BlackBox.scala
+++ b/chiselFrontend/src/main/scala/Chisel/BlackBox.scala
diff --git a/src/main/scala/Chisel/CoreUtil.scala b/chiselFrontend/src/main/scala/Chisel/CoreUtil.scala
index 708b516e..708b516e 100644
--- a/src/main/scala/Chisel/CoreUtil.scala
+++ b/chiselFrontend/src/main/scala/Chisel/CoreUtil.scala
diff --git a/src/main/scala/Chisel/Data.scala b/chiselFrontend/src/main/scala/Chisel/Data.scala
index 8879491c..8879491c 100644
--- a/src/main/scala/Chisel/Data.scala
+++ b/chiselFrontend/src/main/scala/Chisel/Data.scala
diff --git a/src/main/scala/Chisel/Mem.scala b/chiselFrontend/src/main/scala/Chisel/Mem.scala
index 17ac9ca5..17ac9ca5 100644
--- a/src/main/scala/Chisel/Mem.scala
+++ b/chiselFrontend/src/main/scala/Chisel/Mem.scala
diff --git a/src/main/scala/Chisel/Module.scala b/chiselFrontend/src/main/scala/Chisel/Module.scala
index 3e839cac..3e839cac 100644
--- a/src/main/scala/Chisel/Module.scala
+++ b/chiselFrontend/src/main/scala/Chisel/Module.scala
diff --git a/src/main/scala/Chisel/Reg.scala b/chiselFrontend/src/main/scala/Chisel/Reg.scala
index e69061c5..e69061c5 100644
--- a/src/main/scala/Chisel/Reg.scala
+++ b/chiselFrontend/src/main/scala/Chisel/Reg.scala
diff --git a/src/main/scala/Chisel/SeqUtils.scala b/chiselFrontend/src/main/scala/Chisel/SeqUtils.scala
index c63f5735..c63f5735 100644
--- a/src/main/scala/Chisel/SeqUtils.scala
+++ b/chiselFrontend/src/main/scala/Chisel/SeqUtils.scala
diff --git a/src/main/scala/Chisel/When.scala b/chiselFrontend/src/main/scala/Chisel/When.scala
index 5f6b02c5..5f6b02c5 100644
--- a/src/main/scala/Chisel/When.scala
+++ b/chiselFrontend/src/main/scala/Chisel/When.scala
diff --git a/src/main/scala/Chisel/internal/Builder.scala b/chiselFrontend/src/main/scala/Chisel/internal/Builder.scala
index c7ecdaa0..c7ecdaa0 100644
--- a/src/main/scala/Chisel/internal/Builder.scala
+++ b/chiselFrontend/src/main/scala/Chisel/internal/Builder.scala
diff --git a/src/main/scala/Chisel/internal/Error.scala b/chiselFrontend/src/main/scala/Chisel/internal/Error.scala
index 6c4c0880..6c4c0880 100644
--- a/src/main/scala/Chisel/internal/Error.scala
+++ b/chiselFrontend/src/main/scala/Chisel/internal/Error.scala
diff --git a/src/main/scala/Chisel/internal/firrtl/Emitter.scala b/chiselFrontend/src/main/scala/Chisel/internal/firrtl/Emitter.scala
index b690d974..b690d974 100644
--- a/src/main/scala/Chisel/internal/firrtl/Emitter.scala
+++ b/chiselFrontend/src/main/scala/Chisel/internal/firrtl/Emitter.scala
diff --git a/src/main/scala/Chisel/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala
index 1e06a663..1e06a663 100644
--- a/src/main/scala/Chisel/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala