summaryrefslogtreecommitdiff
path: root/chiselFrontend/src/main/scala/Chisel/SeqUtils.scala
blob: c63f57359b26c5a459f54a4a6a28ca4c05260066 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
// See LICENSE for license details.

package Chisel

private[Chisel] object SeqUtils {
  /** Equivalent to Cat(r(n-1), ..., r(0)) */
  def asUInt[T <: Bits](in: Seq[T]): UInt = {
    if (in.tail.isEmpty) {
      in.head.asUInt
    } else {
      val left = asUInt(in.slice(0, in.length/2))
      val right = asUInt(in.slice(in.length/2, in.length))
      right ## left
    }
  }

  /** Counts the number of true Bools in a Seq */
  def count(in: Seq[Bool]): UInt = {
    if (in.size == 0) {
      UInt(0)
    } else if (in.size == 1) {
      in.head
    } else {
      count(in.slice(0, in.size/2)) + (UInt(0) ## count(in.slice(in.size/2, in.size)))
    }
  }

  /** Returns data value corresponding to first true predicate */
  def priorityMux[T <: Bits](in: Seq[(Bool, T)]): T = {
    if (in.size == 1) {
      in.head._2
    } else {
      Mux(in.head._1, in.head._2, priorityMux(in.tail))
    }
  }

  /** Returns data value corresponding to lone true predicate */
  def oneHotMux[T <: Data](in: Iterable[(Bool, T)]): T = {
    if (in.tail.isEmpty) {
      in.head._2
    } else {
      val masked = for ((s, i) <- in) yield Mux(s, i.toBits, Bits(0))
      val width = in.map(_._2.width).reduce(_ max _)
      in.head._2.cloneTypeWidth(width).fromBits(masked.reduceLeft(_|_))
    }
  }
}