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authorAndrew Waterman2015-08-13 16:15:18 -0700
committerAndrew Waterman2015-08-13 16:15:18 -0700
commita69f8ad1a82b60831b40eae4042884f9251ef2c6 (patch)
tree083e9aa76142f66f72f35f38bcc6d68371134e1c /src
parentf676dffc8766ce3d4df390b7c0802ab5b60385a8 (diff)
Add back missing () on toBits declaration
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/Chisel/Core.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala
index d89a4557..e7dce33a 100644
--- a/src/main/scala/Chisel/Core.scala
+++ b/src/main/scala/Chisel/Core.scala
@@ -90,7 +90,7 @@ abstract class Data(dirArg: Direction) extends HasId {
}
wire.asInstanceOf[this.type]
}
- def toBits: UInt = this.flatten.reverse.reduce(_##_)
+ def toBits(): UInt = this.flatten.reverse.reduce(_##_)
def toPort: Port = Port(this, toType)
}