diff options
| -rw-r--r-- | src/main/scala/Chisel/Core.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala index d89a4557..e7dce33a 100644 --- a/src/main/scala/Chisel/Core.scala +++ b/src/main/scala/Chisel/Core.scala @@ -90,7 +90,7 @@ abstract class Data(dirArg: Direction) extends HasId { } wire.asInstanceOf[this.type] } - def toBits: UInt = this.flatten.reverse.reduce(_##_) + def toBits(): UInt = this.flatten.reverse.reduce(_##_) def toPort: Port = Port(this, toType) } |