Move dontTouch, RawModule, and MultiIOModule out of experimental (#1162)

* Move dontTouch out of experimental package.

* Move RawModule, MultiIOModule out of experimental.

* Respond to comments - Move LagacyModule from experimental to internal.
*NOTE*: At some point, these module definitions (especially those in separate packages) should be moved to individual files at the appropriate location in the source tree. The current organization is purely to support comparison with prior versions.

* Fix up a few more imports.

26 files changed, 14 insertions, 30 deletions

diff --git a/src/test/scala/chiselTests/AnalogSpec.scala b/src/test/scala/chiselTests/AnalogSpec.scala
index c78c8c0e..d81ed009 100644
--- a/src/test/scala/chiselTests/AnalogSpec.scala
+++ b/src/test/scala/chiselTests/AnalogSpec.scala
@@ -5,7 +5,7 @@ package chiselTests
 import chisel3._
 import chisel3.util._
 import chisel3.testers.BasicTester
-import chisel3.experimental.{Analog, attach, BaseModule, RawModule}
+import chisel3.experimental.{Analog, attach, BaseModule}
 
 // IO for Modules that just connect bus to out
 class AnalogReaderIO extends Bundle {
diff --git a/src/test/scala/chiselTests/BoringUtilsSpec.scala b/src/test/scala/chiselTests/BoringUtilsSpec.scala
index 70bd0166..856f6b91 100644
--- a/src/test/scala/chiselTests/BoringUtilsSpec.scala
+++ b/src/test/scala/chiselTests/BoringUtilsSpec.scala
@@ -5,7 +5,7 @@ package chiselTests
 import chisel3._
 import chisel3.util.Counter
 import chisel3.testers.BasicTester
-import chisel3.experimental.{BaseModule, ChiselAnnotation, MultiIOModule, RawModule, RunFirrtlTransform}
+import chisel3.experimental.{BaseModule, ChiselAnnotation, RunFirrtlTransform}
 import chisel3.util.experimental.BoringUtils
 
 import firrtl.{CircuitForm, CircuitState, ChirrtlForm, Transform}
diff --git a/src/test/scala/chiselTests/BundleLiteralSpec.scala b/src/test/scala/chiselTests/BundleLiteralSpec.scala
index aa1dbc0f..ec0bad66 100644
--- a/src/test/scala/chiselTests/BundleLiteralSpec.scala
+++ b/src/test/scala/chiselTests/BundleLiteralSpec.scala
@@ -4,7 +4,6 @@ package chiselTests
 
 import chisel3._
 import chisel3.testers.BasicTester
-import chisel3.experimental.RawModule
 import chisel3.experimental.BundleLiterals._
 import chisel3.experimental.BundleLiteralException
 
diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala
index d0a1f5c5..9af7e88f 100644
--- a/src/test/scala/chiselTests/ChiselSpec.scala
+++ b/src/test/scala/chiselTests/ChiselSpec.scala
@@ -6,7 +6,6 @@ import org.scalatest._
 import org.scalatest.prop._
 import org.scalacheck._
 import chisel3._
-import chisel3.experimental.RawModule
 import chisel3.testers._
 import firrtl.options.OptionsException
 import firrtl.{AnnotationSeq, CommonOptions, ExecutionOptionsManager, FirrtlExecutionFailure, FirrtlExecutionSuccess, HasFirrtlOptions}
diff --git a/src/test/scala/chiselTests/Clock.scala b/src/test/scala/chiselTests/Clock.scala
index f508bb81..58a491ef 100644
--- a/src/test/scala/chiselTests/Clock.scala
+++ b/src/test/scala/chiselTests/Clock.scala
@@ -3,7 +3,6 @@
 package chiselTests
 
 import chisel3._
-import chisel3.experimental.RawModule
 import chisel3.testers.BasicTester
 
 class ClockAsUIntTester extends BasicTester {
diff --git a/src/test/scala/chiselTests/CloneModuleSpec.scala b/src/test/scala/chiselTests/CloneModuleSpec.scala
index ca8bd007..b3bc2b16 100644
--- a/src/test/scala/chiselTests/CloneModuleSpec.scala
+++ b/src/test/scala/chiselTests/CloneModuleSpec.scala
@@ -4,7 +4,7 @@ package chiselTests
 
 import chisel3._
 import chisel3.util.{Queue, EnqIO, DeqIO, QueueIO, log2Ceil}
-import chisel3.experimental.{CloneModuleAsRecord, IO, MultiIOModule}
+import chisel3.experimental.{CloneModuleAsRecord, IO}
 import chisel3.testers.BasicTester
 
 class MultiIOQueue[T <: Data](gen: T, val entries: Int) extends MultiIOModule {
diff --git a/src/test/scala/chiselTests/DataPrint.scala b/src/test/scala/chiselTests/DataPrint.scala
index 57e44c36..493d3c7a 100644
--- a/src/test/scala/chiselTests/DataPrint.scala
+++ b/src/test/scala/chiselTests/DataPrint.scala
@@ -5,7 +5,7 @@ package chiselTests
 import org.scalatest._
 
 import chisel3._
-import chisel3.experimental.{ChiselEnum, FixedPoint, RawModule, MultiIOModule}
+import chisel3.experimental.{ChiselEnum, FixedPoint}
 import chisel3.experimental.BundleLiterals._
 
 class DataPrintSpec extends ChiselFlatSpec with Matchers {
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index 4c5e819d..1e536a5a 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -4,7 +4,6 @@ package chiselTests
 
 import org.scalatest._
 import chisel3._
-import chisel3.experimental.RawModule
 
 class DirectionedBundle extends Bundle {
   val in = Input(UInt(32.W))
@@ -127,7 +126,7 @@ class DirectionSpec extends ChiselPropSpec with Matchers {
     }
   }
 
-  import chisel3.experimental.{MultiIOModule, DataMirror, Direction, RawModule}
+  import chisel3.experimental.{DataMirror, Direction}
 
   property("Directions should be preserved through cloning and binding of Bundles") {
     elaborate(new MultiIOModule {
diff --git a/src/test/scala/chiselTests/DontTouchSpec.scala b/src/test/scala/chiselTests/DontTouchSpec.scala
index 4b1bce8e..ead4ffc9 100644
--- a/src/test/scala/chiselTests/DontTouchSpec.scala
+++ b/src/test/scala/chiselTests/DontTouchSpec.scala
@@ -3,7 +3,6 @@
 package chiselTests
 
 import chisel3._
-import chisel3.experimental.dontTouch
 
 class HasDeadCodeChild(withDontTouch: Boolean) extends Module {
   val io = IO(new Bundle {
diff --git a/src/test/scala/chiselTests/DriverSpec.scala b/src/test/scala/chiselTests/DriverSpec.scala
index 75ab93ae..7190261c 100644
--- a/src/test/scala/chiselTests/DriverSpec.scala
+++ b/src/test/scala/chiselTests/DriverSpec.scala
@@ -17,7 +17,7 @@ class DummyModule extends Module {
   io.out := io.in
 }
 
-class TypeErrorModule extends chisel3.experimental.MultiIOModule {
+class TypeErrorModule extends chisel3.MultiIOModule {
   val in = IO(Input(UInt(1.W)))
   val out = IO(Output(SInt(1.W)))
   out := in
diff --git a/src/test/scala/chiselTests/LiteralExtractorSpec.scala b/src/test/scala/chiselTests/LiteralExtractorSpec.scala
index 533de888..b56672af 100644
--- a/src/test/scala/chiselTests/LiteralExtractorSpec.scala
+++ b/src/test/scala/chiselTests/LiteralExtractorSpec.scala
@@ -3,7 +3,7 @@
 package chiselTests
 
 import chisel3._
-import chisel3.experimental.{FixedPoint, RawModule}
+import chisel3.experimental.FixedPoint
 import chisel3.experimental.BundleLiterals._
 import chisel3.testers.BasicTester
 
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index ed624f0c..f730d08b 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -142,7 +142,7 @@ class ModuleSpec extends ChiselPropSpec {
   property("DataMirror.modulePorts should work") {
     elaborate(new Module {
       val io = IO(new Bundle { })
-      val m = Module(new chisel3.experimental.MultiIOModule {
+      val m = Module(new chisel3.MultiIOModule {
         val a = IO(UInt(8.W))
         val b = IO(Bool())
       })
diff --git a/src/test/scala/chiselTests/MultiIOModule.scala b/src/test/scala/chiselTests/MultiIOModule.scala
index 7978970a..e15acc31 100644
--- a/src/test/scala/chiselTests/MultiIOModule.scala
+++ b/src/test/scala/chiselTests/MultiIOModule.scala
@@ -3,7 +3,6 @@
 package chiselTests
 
 import chisel3._
-import chisel3.experimental.MultiIOModule
 import chisel3.testers.BasicTester
 
 class MultiIOPlusOne extends MultiIOModule {
diff --git a/src/test/scala/chiselTests/NamingAnnotationTest.scala b/src/test/scala/chiselTests/NamingAnnotationTest.scala
index 82a5c109..4576176a 100644
--- a/src/test/scala/chiselTests/NamingAnnotationTest.scala
+++ b/src/test/scala/chiselTests/NamingAnnotationTest.scala
@@ -3,7 +3,7 @@
 package chiselTests
 
 import chisel3._
-import chisel3.experimental.{MultiIOModule, chiselName}
+import chisel3.experimental.chiselName
 import chisel3.internal.InstanceId
 
 import scala.collection.mutable.ListBuffer
diff --git a/src/test/scala/chiselTests/RawModuleSpec.scala b/src/test/scala/chiselTests/RawModuleSpec.scala
index 88b53457..45d6b58a 100644
--- a/src/test/scala/chiselTests/RawModuleSpec.scala
+++ b/src/test/scala/chiselTests/RawModuleSpec.scala
@@ -3,7 +3,6 @@
 package chiselTests
 
 import chisel3._
-import chisel3.experimental.RawModule
 import chisel3.testers.BasicTester
 
 class UnclockedPlusOne extends RawModule {
diff --git a/src/test/scala/chiselTests/ResetSpec.scala b/src/test/scala/chiselTests/ResetSpec.scala
index 297c5516..2381aadc 100644
--- a/src/test/scala/chiselTests/ResetSpec.scala
+++ b/src/test/scala/chiselTests/ResetSpec.scala
@@ -3,7 +3,6 @@
 package chiselTests
 
 import chisel3._
-import chisel3.experimental.{IO, RawModule}
 import chisel3.util.{Counter, Queue}
 import chisel3.testers.BasicTester
 
diff --git a/src/test/scala/chiselTests/TransitNameSpec.scala b/src/test/scala/chiselTests/TransitNameSpec.scala
index 857d6470..7c5f0578 100644
--- a/src/test/scala/chiselTests/TransitNameSpec.scala
+++ b/src/test/scala/chiselTests/TransitNameSpec.scala
@@ -4,7 +4,6 @@ package chiselTests
 import org.scalatest.{FlatSpec, Matchers}
 
 import chisel3._
-import chisel3.experimental.RawModule
 import chisel3.util.TransitName
 
 import firrtl.FirrtlExecutionSuccess
diff --git a/src/test/scala/chiselTests/Util.scala b/src/test/scala/chiselTests/Util.scala
index 82ae7072..f71cd7f3 100644
--- a/src/test/scala/chiselTests/Util.scala
+++ b/src/test/scala/chiselTests/Util.scala
@@ -5,7 +5,6 @@
 package chiselTests
 
 import chisel3._
-import chisel3.experimental._
 
 class PassthroughModuleIO extends Bundle {
   val in = Input(UInt(32.W))
diff --git a/src/test/scala/chiselTests/aop/SelectSpec.scala b/src/test/scala/chiselTests/aop/SelectSpec.scala
index d3f72551..f3c756ab 100644
--- a/src/test/scala/chiselTests/aop/SelectSpec.scala
+++ b/src/test/scala/chiselTests/aop/SelectSpec.scala
@@ -7,7 +7,6 @@ import chiselTests.ChiselFlatSpec
 import chisel3._
 import chisel3.aop.Select.{PredicatedConnect, When, WhenNot}
 import chisel3.aop.{Aspect, Select}
-import chisel3.experimental.RawModule
 import firrtl.{AnnotationSeq}
 
 import scala.reflect.runtime.universe.TypeTag
diff --git a/src/test/scala/chiselTests/experimental/ProgrammaticPortsSpec.scala b/src/test/scala/chiselTests/experimental/ProgrammaticPortsSpec.scala
index d17bfd32..09e401f2 100644
--- a/src/test/scala/chiselTests/experimental/ProgrammaticPortsSpec.scala
+++ b/src/test/scala/chiselTests/experimental/ProgrammaticPortsSpec.scala
@@ -4,7 +4,6 @@ package chiselTests
 package experimental
 
 import chisel3._
-import chisel3.experimental.MultiIOModule
 
 // NOTE This is currently an experimental API and subject to change
 // Example using a private port
diff --git a/src/test/scala/chiselTests/stage/ChiselAnnotationsSpec.scala b/src/test/scala/chiselTests/stage/ChiselAnnotationsSpec.scala
index 63b1001f..dd0dd09a 100644
--- a/src/test/scala/chiselTests/stage/ChiselAnnotationsSpec.scala
+++ b/src/test/scala/chiselTests/stage/ChiselAnnotationsSpec.scala
@@ -5,7 +5,6 @@ package chiselTests.stage
 import org.scalatest.{FlatSpec, Matchers}
 import chisel3._
 import chisel3.stage.{ChiselCircuitAnnotation, ChiselGeneratorAnnotation, DesignAnnotation}
-import chisel3.experimental.RawModule
 import firrtl.options.OptionsException
 
 class ChiselAnnotationsSpecFoo extends RawModule {
diff --git a/src/test/scala/chiselTests/stage/ChiselMainSpec.scala b/src/test/scala/chiselTests/stage/ChiselMainSpec.scala
index 27a3093c..7862acd6 100644
--- a/src/test/scala/chiselTests/stage/ChiselMainSpec.scala
+++ b/src/test/scala/chiselTests/stage/ChiselMainSpec.scala
@@ -3,10 +3,7 @@
 package chiselTests.stage
 
 import chisel3._
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselMain}
-import chisel3.experimental.RawModule
-
-import firrtl.AnnotationSeq
+import chisel3.stage.ChiselMain
 
 import java.io.File
 
diff --git a/src/test/scala/chiselTests/stage/phases/AddImplicitOutputAnnotationFileSpec.scala b/src/test/scala/chiselTests/stage/phases/AddImplicitOutputAnnotationFileSpec.scala
index f5fe0440..734f571a 100644
--- a/src/test/scala/chiselTests/stage/phases/AddImplicitOutputAnnotationFileSpec.scala
+++ b/src/test/scala/chiselTests/stage/phases/AddImplicitOutputAnnotationFileSpec.scala
@@ -4,7 +4,7 @@ package chiselTests.stage.phases
 
 import org.scalatest.{FlatSpec, Matchers}
 
-import chisel3.experimental.RawModule
+import chisel3.RawModule
 import chisel3.stage.ChiselGeneratorAnnotation
 import chisel3.stage.phases.{AddImplicitOutputAnnotationFile, Elaborate}
 
diff --git a/src/test/scala/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala b/src/test/scala/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala
index 411aa6ba..1a667365 100644
--- a/src/test/scala/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala
+++ b/src/test/scala/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala
@@ -4,7 +4,7 @@ package chiselTests.stage.phases
 
 import org.scalatest.{FlatSpec, Matchers}
 
-import chisel3.experimental.RawModule
+import chisel3.RawModule
 import chisel3.stage.{ChiselGeneratorAnnotation, ChiselOutputFileAnnotation}
 import chisel3.stage.phases.{AddImplicitOutputFile, Elaborate}
 
diff --git a/src/test/scala/chiselTests/stage/phases/ConvertSpec.scala b/src/test/scala/chiselTests/stage/phases/ConvertSpec.scala
index 30fad4f5..1eefcdb6 100644
--- a/src/test/scala/chiselTests/stage/phases/ConvertSpec.scala
+++ b/src/test/scala/chiselTests/stage/phases/ConvertSpec.scala
@@ -5,7 +5,7 @@ package chiselTests.stage.phases
 import org.scalatest.{FlatSpec, Matchers}
 
 import chisel3._
-import chisel3.experimental.{ChiselAnnotation, RawModule, RunFirrtlTransform}
+import chisel3.experimental.{ChiselAnnotation, RunFirrtlTransform}
 import chisel3.stage.ChiselGeneratorAnnotation
 import chisel3.stage.phases.{Convert, Elaborate}
 
diff --git a/src/test/scala/chiselTests/stage/phases/EmitterSpec.scala b/src/test/scala/chiselTests/stage/phases/EmitterSpec.scala
index 63498adb..a421e9cc 100644
--- a/src/test/scala/chiselTests/stage/phases/EmitterSpec.scala
+++ b/src/test/scala/chiselTests/stage/phases/EmitterSpec.scala
@@ -4,7 +4,7 @@ package chiselTests.stage.phases
 
 import org.scalatest.{FlatSpec, Matchers}
 
-import chisel3.experimental.RawModule
+import chisel3.RawModule
 import chisel3.stage.{ChiselCircuitAnnotation, ChiselGeneratorAnnotation, ChiselOutputFileAnnotation}
 import chisel3.stage.phases.{Convert, Elaborate, Emitter}